Epson S1C17624 Technical Manual page 184

17 WaTChDOG TiMeR (WDT)
17.3.3 WDT Reset
To reset WDT, write 1 to WDTRST/WDT_CTL register.
A location should be provided for periodically processing the routine for resetting WDT before an NMI or reset
is generated when using WDT. Process this routine within 131,072/f
kHz) cycle.
After resetting, WDT starts counting with a new NMI/Reset generation cycle.
If WDT is not reset within the NMI/Reset generation cycle for any reason, the CPU is switched to interrupt pro-
cessing by NMI or reset, the interrupt vector is read out, and the interrupt handler routine is executed. The reset and
NMI vector addresses are TTBR + 0x0 and TTBR + 0x08.
If the counter overflows and generates an NMI without WDT being reset, WDTST/WDT_ST register is set to 1.
This bit is provided to confirm that WDT was the source of the NMI. The WDTST set to 1 is cleared to 0 by reset-
ting WDT.
17.3.4 Operations in halT and SleeP Modes
halT mode
The WDT module operates in HALT mode, as the clock is supplied. HALT mode is therefore cleared by an NMI or
reset if it continues for more than the NMI/reset generation cycle. To disable WDT while in HALT mode, stop WDT
by writing 0b1010 to WDTRUN[3:0]/WDT_CTL register before executing the halt instruction. Reset WDT before
resuming operations after HALT mode is cleared.
SleeP mode
The clock supplied from the CLG module is stopped in SLEEP mode, which also stops WDT. To prevent generation
of an unnecessary NMI or reset after clearing SLEEP mode, reset WDT before executing the slp instruction. WDT
should also be stopped as required using WDTRUN[3:0].
17.4 Control Register Details
address
0x5040 WDT_CTL
0x5041 WDT_ST
The WDT registers are described in detail below. These are 8-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
Watchdog Timer Control Register (WDT_CTl)
Register name address Bit
Watchdog 0x5040 D7–5 –
Timer Control
(8 bits)
D4
Register
D3–0 WDTRun[3:0] Watchdog timer run/stop control
(WDT_CTl)
D[7:5] Reserved
D4 WDTRST: Watchdog Timer Reset Bit
Resets WDT.
1 (W): Reset
0 (W): Ignored
0 (R): Always 0 when read (default)
note: To use WDT, it must be reset by writing 1 to this bit within the NMI/reset generation cycle (4
seconds when f
new NMI/reset generation cycle.
17-2
Table 17.4.1 List of WDT Registers
Register name
Watchdog Timer Control Register
Watchdog Timer Status Register
name Function
reserved
WDTRST
Watchdog timer reset
= 32.768 kHz). This resets the up-counter to 0 and starts counting with a
OSC1
Seiko epson Corporation
second (4 seconds when f
OSC1
Function
Resets and starts/stops the timer.
Sets the timer mode and indicates NMI status.
Setting init. R/W
–
1 Reset 0 Ignored
Other than 1010 1010 1010 R/W
Run Stop
S1C17624/604/622/602/621 TeChniCal Manual
= 32.768
OSC1
Remarks
– – 0 when being read.
0 W