Epson S1C17624 Technical Manual page 335

0x5063, 0x50a0–0x50a6
Register name address Bit
lCD Clock 0x5063 D7–5 –
Select Register
(8 bits) D4–2 lCKDV[2:0] LCD clock division ratio select
(OSC_lClK)
D1
D0
lCD Display 0x50a0
D7
Control Register (8 bits)
D6
(lCD_DCTl)
D5
D4
D3–2 –
D1–0 DSPC[1:0]
lCD Contrast 0x50a1 D7–4 –
adjustment (8 bits)
D3–0 lC[3:0]
Register
(lCD_CaDJ)
lCD Clock 0x50a2 D7–6 FRMCnT[1:0] Frame frequency control
Control Register
(8 bits)
(lCD_CCTl)
D5
D4–3 –
D2–0 lDuTY[2:0] LCD duty select
lCD Voltage 0x50a3 D7–5 –
Regulator
(8 bits)
D4
Control Register
D3–1 –
(lCD_VReG)
D0
lCD interrupt 0x50a5 D7–1 –
Mask Register
(8 bits)
(lCD_iMSK) D0
lCD interrupt 0x50a6 D7–1 –
Flag Register
(8 bits)
(lCD_iFlG) D0
0x5065, 0x50c0–0x50c5
Register name address Bit
T8OSC1 Clock 0x5065 D7–4 –
Control Register (8 bits) D3–1 T8O1CK
(OSC_T8OSC1)
D0
T8OSC1 0x50c0 D7–5 –
Control Register
(8 bits)
D4
(T8OSC1_CTl)
D3–2 –
D1
D0
T8OSC1 0x50c1 D7–0 T8OCnT[7:0] Timer counter data
Counter Data
(8 bits)
Register
(T8OSC1_CnT)
S1C17624/604/622/602/621 TeChniCal Manual
name Function
reserved
lCKSRC LCD clock source select
lCKen
LCD clock enable
SeGReV
Segment output assignment control 1 Normal
COMReV Common output assignment control 1 Normal
DSPaR
Display memory area control
DSPReV
Reverse display control
reserved
LCD display control
reserved
LCD contrast adjustment
lFROuT
LFRO output control
reserved
reserved
lhVlD
LCD heavy load protection mode
reserved
VCSel V reference voltage select
C
reserved
FRMie Frame signal interrupt enable
reserved
FRMiF Frame signal interrupt flag
name Function
reserved
T8OSC1 clock division ratio select T8O1CK[2:0]
[2:0]
T8O1Ce Clock enable
reserved
T8ORST
Timer reset
reserved
T8ORMD
Count mode select
T8ORun Timer run/stop control
T8OCNT7 = MSB
T8OCNT0 = LSB
Seiko epson Corporation
aPPenDiX a liST OF i/O ReGiSTeRS
Setting init. R/W
–
LCKDV[2:0] Division ratio 0x0 R/W When the clock
0x7–0x5 reserved
0x4 1/512
0x3 1/256
0x2 1/128
0x1 1/64
0x0 1/32
1 OSC1 0 HSCLK
1 Enable 0 Disable
0 Reverse
0 Reverse
1 Area 1 0 Area 0
1 Normal 0 Reverse
–
DSPC[1:0] Display 0x0 R/W
0x3 All off
0x2 All on
0x1 Normal display
0x0 Display off
–
LC[3:0] Display 0x7 R/W
0xf Dark
: :
0x0 Light
FRMCNT[1:0] Division ratio 0x1 R/W Source clock: LCLK
0x3 1/1024
0x2 1/680
0x1 1/512
0x0 1/256
1 On 0 Off
–
LDUTY[2:0] Duty 0x4 R/W
0x7–0x5 reserved
0x4 1/8
0x3 1/4
0x2 1/3
0x1 1/2
0x0 Static
–
1 On 0 Off
–
1 V 0 V
C2 C1
–
1 Enable 0 Disable
–
1 Occurred 0 Not occurred
Setting init. R/W
–
Division ratio 0x0 R/W Clock source: OSC1
0x7–0x6 reserved
0x5 1/32
0x4 1/16
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
1 Enable 0 Disable
–
1 Reset 0 Ignored
–
1 One shot 0 Repeat
1 Run 0 Stop
0x0 to 0xff 0x0
lCD Driver
Remarks
– – 0 when being read.
source is HSCLK
1 R/W
0 R/W
1 R/W
1 R/W
0 R/W
1 R/W
– – 0 when being read.
– – 0 when being read.
0 R/W
– – 0 when being read.
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W Reset by writing 1.
8-bit OSC1 Timer
Remarks
– – 0 when being read.
0 R/W
– – 0 when being read.
0 W
– –
0 R/W
0 R/W
R
aP-a-13