Epson S1C17624 Technical Manual page 60

7 Clock Generator (CLG)
7.1 ClG Module Overview
The clock generator (CLG) controls the internal oscillators and the system clocks to be supplied to the S1C17 Core,
on-chip peripheral modules, and external devices.
The features of the CLG module are listed below.
• Generates the operating clocks with the built-in oscillators.
- IOSC oscillator circuit: 2.7 MHz (typ.)
- OSC3 oscillator circuit: 8.2 MHz (max.) crystal or ceramic oscillator circuit
- OSC1 oscillator circuit: 32.768 kHz (typ.) crystal oscillator circuit
• Switches the system clock. The system clock source can be selected from IOSC, OSC3, and OSC1 via software.
• Generates the CPU core clock (CCLK) and controls the clock supply to the core block. The CCLK frequency can
be selected from system clock × 1/1, 1/2, 1/4, and 1/8.
• Controls the clock supply to the peripheral modules.
• Turns the clocks on and off according to the CPU operating status (RUN, HALT, or SLEEP).
• Controls two clock outputs to external devices.
Figure 7.1.1 shows the clock system and CLG module configuration.
IOSC
oscillator
(2.7 MHz)
OSC3
OSC3
oscillator
OSC4
(8.2 MHz)
OSC1
OSC1
oscillator
OSC2
(32.768 kHz)
FOUT1
FOUT1
output circuit
FOUTH
FOUTH
output circuit
RESET
NMI
To reduce current consumption, control the clock in conjunction with processing and use HALT and SLEEP modes.
For more information on reducing current consumption, see "Power Saving" in the appendix chapter.
S1C17624/604/622/602/621 TeChniCal Manual
Supports an external clock input.
Wait circuit
IOSC
Wait circuit
OSC3
Wait circuit
OSC1
Divider
HSCLK
Figure 7. 1.1 CLG Module Configuration
Seiko epson Corporation
HSCLK
Clock gear
SYSCLK
OSC1
(1/1–1/8)
OSC1
Divider
Noise filter
Noise filter
7 ClOCK GeneRaTOR (ClG)
ClG
HALT
Gate S1C17 Core
CCLK
T16, T8F, T16E,
UART, SPI, I2CM,
Gate PCLK
I2CS, P, MISC,
VD1, SVD, REMC,
ADC10, ITC
Gate RTC*
CT, SWT, WDT
256 Hz
LCD, SVD, RFC,
T8OSC1, T16A2*
* S1C17624/604 only
To internal circuits
To S1C17 Core
7-1