Epson S1C17624 Technical Manual page 264

Table 24.
24.3.2 Selecting a/D Conversion Start and end Channels
Select the channel in which the A/D conversion is to be performed from among the pins (channels) that have been
set for analog input. To enable A/D conversions in multiple channels to be performed successively through one con-
vert operation, specify the conversion start and conversion end channels using ADCS[2:0]/ADC10_TRG register
and ADCE[2:0]/ADC10_TRG register, respectively.
Table 24.
Example: Operation of one A/D conversion
ADCS[2:0] = 0, ADCE[2:0] = 0
Converted only in AIN0
ADCS[2:0] = 0, ADCE[2:0] = 3
Converted in the following order: AIN0→AIN1→AIN2→AIN3
ADCS[2:0] = 2, ADCE[2:0] = 1
Converted in the following order: AIN2→AIN3→AIN4→AIN5→AIN6→AIN7→AIN0→AIN1
24.3.3 a/D Conversion Mode Setting
The A/D converter provides two conversion modes that can be selected using ADMS/ADC10_TRG register: one-
time conversion mode and continuous conversion mode.
1. One-time conversion mode (aDMS = 0)
The A/D converter performs A/D conversion for all analog inputs within the range from the start channel speci-
fied by ADCS[2:0]/ADC10_TRG register to the end channel specified by the ADCE[2:0]/ADC10_TRG register
once and then stops automatically.
S1C17624/604/622/602/621 TeChniCal Manual
3.1.1 A/D Conversion Clock (PCLK Division Ratio) Selection
aDDF[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
3.2.1 Relationship between ADCS/ADCE and Input Channels
aDCS[2:0]/aDCe[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko epson Corporation
24 a/D COnVeRTeR (aDC10)
Division ratio
Reserved
1/32768
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
(Default: 0x0)
Channel selected
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
(Default: 0x0)
24-3