Epson S1C17624 Technical Manual page 186

18 UART
18.1 uaRT Module Overview
The S1C17624/604/622/602/621 includes a UART module with two asynchronous communication channels. It
includes a 2-byte receive data buffer and 1-byte transmit data buffer allowing successive data transfer. The UART
module also includes an RZI modulator/demodulator circuit that enables IrDA 1.0-compatible infrared communica-
tions simply by adding basic external circuits.
The following shows the main features of the UART:
• Transfer rate: 150 to 460,800 bps (150 to 115,200 bps in IrDA mode)
• Transfer clock: Internal clock (T8F output) or an external clock (SCLK input) can be selected.
• Character length: 7 or 8 bits (LSB first)
• Parity mode: Even, odd, or no parity
• Stop bit: 1 or 2 bits
• Start bit: 1 bit fixed
• Supports full-duplex communications.
• Includes a 2-byte receive data buffer and a 1-byte transmit data buffer.
• Includes an RZI modulator/demodulator circuit to support IrDA 1.0-compatible infrared communications.
• Can detect parity error, framing error, and overrun error during receiving.
• Can generate receive buffer full, transmit buffer empty, and receive error interrupts.
Figure 18.1.1 shows the UART configuration.
Ch.0: from T8F Ch.0
sclk
Ch.1: from T8F Ch.1
Bus I/F
Internal bus
registers
Interrupt
ITC
note: Two channels in the UART module have the same functions except for control register addresses.
For this reason, the description in this chapter applies to both UART channels. The 'x' in the regis-
ter and pin names indicate a channel number (0 or 1).
Example: UART_CTLx register
Ch.0: UART_CTL0 register
Ch.1: UART_CTL1 register
S1C17624/604/622/602/621 TeChniCal Manual
Receive data
buffer (2 bytes)
and
control
Transmit data
control buffer (1 byte)
Figure 18.1.1 UART Configuration
Seiko epson Corporation
Shift register
demodulator
Clock/transfer control
Shift register
modulator
18 uaRT
RZI
Ch.0: SIN0
Ch.1: SIN1
Ch.0: SCLK0
Ch.1: SCLK1
RZI
Ch.0: SOUT0
Ch.1: SOUT1
UART Ch.x
18-1