Table of Contents
Advertisement
aPPenDiX C MOunTinG PReCauTiOnS
Power supply circuit
Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues.
(1) Connections from the power supply to the V
est patterns possible.
(2) If a bypass capacitor is connected between V
be as short as possible.
Signal line location
• To prevent electromagnetically-induced noise arising from mutual induction, large-current signal lines should
not be positioned close to circuits susceptible to noise, such as oscillators.
• Locating signal lines in parallel over significant distances or crossing signal lines operating at high speed will
cause malfunctions due to noise generated by mutual interference. Specifically, avoid positioning crossing
signal lines operating at high speed close to circuits susceptible to noise, such as oscillators.
noise-induced malfunctions
Check the following three points if you suspect the presence of noise-induced IC malfunctions.
(1) DSIO pin
Low-level noise to this pin will cause a switch to debug mode. The switch to debug mode can be confirmed
by the clock output from DCLK and a High signal from the DST2 pin.
For the product version, we recommend connecting the DSIO pin directly to V
pin using a resistor not exceeding 10 kW. The IC includes an internal pull-up resistor. The resistor has a
relatively high impedance of 100 kW to 500 kW and is not noise-resistant.
(2) #RESET pin
Low-level noise to this pin will reset the IC. Depending on the input waveform, the reset may not proceed
correctly. This is more likely to occur if, due to circuit design choices, the impedance is high when the reset
input is High.
(3) V
and V
power supply
DD
SS
The IC will malfunction at the instant when noise falling below the rated voltage is input. Incorporate coun-
termeasures on the circuit board, including close patterns for circuit board power supply circuits, noise-
filtering decoupling capacitors, and surge/noise prevention components on the power supply line.
Perform the inspections described above using an oscilloscope capable of observing waveforms of at least 200
MHz. It may not be possible to observe high-speed noise events with a low-speed oscilloscope.
aP-C-2
and V
DD
and V
DD
Bypass capacitor connection example
V
DD
V
SS
Prohibited pattern
Large current signal line
High-speed signal line
Seiko epson Corporation
pins should be implemented via the shortest, thick-
SS
, connections between the V
SS
V
DD
V
SS
OSC1, OSC3
OSC2, OSC4
V
SS
S1C17624/604/622/602/621 TeChniCal Manual
and V
pins should
DD
SS
or pulling up the DISO
DD
Advertisement
Table of Contents
