Epson S1C17624 Technical Manual page 160

D8 CCBMD: T16a_CCB Register Mode Select Bit
Selects the T16A_CCBx register function (comparator mode or capture mode).
1 (R/W): Capture mode
0 (R/W): Comparator mode (default)
Writing 1 to CCBMD configures the T16A_CCBx register as the capture B register (capture mode) to
which the counter data will be loaded by the external trigger signal. When CCBMD is 0, the T16A_
CCBx register functions as the compare B register (comparator mode) for writing a comparison value to
generate the compare B signal.
D[7:6] CaPaTRG[1:0]: Capture a Trigger Select Bits
Selects the trigger edge(s) of the external signal (CAPAx) at which the counter value is captured in the
capture A register.
CAPATRG[1:0] are control bits for capture mode and are ineffective in comparator mode.
D[5:4] TOuTaMD[1:0]: TOuT a Mode Select Bits
Configures how the TOUT A signal waveform (TOUTAx output) is changed by the compare A and
compare B signals. These bits are also used to turn the TOUT A output On and Off.
TOUTAMD[1:0] are control bits for comparator mode and are ineffective in capture mode.
D[3:2] Reserved
D1 TOuTainV: TOuT a invert Bit
Selects the TOUT A signal (TOUTAx output) polarity.
1 (R/W): Inverted (active Low)
0 (R/W): Normal (active High) (default)
Writing 1 to TOUTAINV generates an active Low signal (Off level = High) for the TOUT A output.
When TOUTAINV is 0, an active High signal (Off level = Low) is generated.
TOUTAINV is a control bit for comparator mode and is ineffective in capture mode.
D0 CCaMD: T16a_CCa Register Mode Select Bit
Selects the T16A_CCAx register function (comparator mode or capture mode).
1 (R/W): Capture mode
0 (R/W): Comparator mode (default)
Writing 1 to CCAMD configures the T16A_CCAx register as the capture A register (capture mode) to
which the counter data will be loaded by the external trigger signal. When CCAMD is 0, the T16A_
CCAx register functions as the compare A register (comparator mode) for writing a comparison value
to generate the compare A signal.
S1C17624/604/622/602/621 TeChniCal Manual
Table 13. 8.7 Capture A Trigger Edge Selection
CaPaTRG[1:0]
0x3
0x2
0x1
0x0
Table 13. 8.8 TOUT A Generation Mode
TOuTaMD[1:0] When compare a occurs When compare B occurs
0x3 No change
0x2
0x1
0x0
Seiko epson Corporation
Trigger edge
Falling edge and rising edge
Falling edge
Rising edge
Not triggered
Toggle
Toggle No change
Rise Fall
Disable output
13 16-BiT PWM TiMeRS (T16a2)
(Default: 0x0)
(Default: 0x0)
13-17