Epson S1C17624 Technical Manual page 37

Classification
Branch retd
System control nop
halt
slp
ei
di
Coprocessor control ld.cw
ld.ca
ld.cf
*1 The ld.a instruction accesses memories in 32-bit length. During data transfer from a register to a memory, the
32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memory,
the eight high-order bits of the read data are ignored.
The symbols in the above table each have the meanings specified below.
Symbol
%rs
%rd
[%rb]
[%rb]+
[%rb]-
-[%rb]
%sp
[%sp],[%sp+imm7]
[%sp]+
[%sp]-
-[%sp]
imm3,imm5,imm7,imm13
sign7,sign10
2.4 Reading PSR
The S1C17624/604/622/602/621 includes the MISC_PSR register for reading the contents of the PSR (Processor
Status Register) in the S1C17 Core. Reading the contents of this register makes it possible to check the contents of
the PSR using the application software. Note that data cannot be written to the PSR.
PSR Register (MiSC_PSR)
Register name address Bit
PSR Register 0x532c D15–8 –
(MiSC_PSR)
(16 bits) D7–5 PSRil[2:0] PSR interrupt level (IL) bits
D4
D3
D2
D1
D0
D[15:8] Reserved
D[7:5] PSRil[2:0]: PSR interrupt level (il) Bits
The value of the PSR IL (interrupt level) bits can be read out. (Default: 0x0)
D4 PSRie: PSR interrupt enable (ie) Bit
The value of the PSR IE (interrupt enable) bit can be read out.
1 (R): 1 (interrupt enabled)
0 (R): 0 (interrupt disabled) (default)
S1C17624/604/622/602/621 TeChniCal Manual
Mnemonic
Return from debug processing
No operation
HALT mode
SLEEP mode
Enable interrupts
Disable interrupts
Transfer data to coprocessor
%rd,%rs
%rd,imm7
%rd,%rs Transfer data to coprocessor and get results and flag statuses
%rd,imm7
Transfer data to coprocessor and get flag statuses
%rd,%rs
%rd,imm7
Table 2. 3.2 Symbol Meanings
General-purpose register, source
General-purpose register, destination
Memory addressed by general-purpose register
Memory addressed by general-purpose register with address post-incremented
Memory addressed by general-purpose register with address post-decremented
Memory addressed by general-purpose register with address pre-decremented
Stack pointer
Stack
Stack with address post-incremented
Stack with address post-decremented
Stack with address pre-decremented
Unsigned immediate (numerals indicating bit length)
Signed immediate (numerals indicating bit length)
name Function
reserved
PSRie
PSR interrupt enable (IE) bit
PSRC
PSR carry (C) flag
PSRV
PSR overflow (V) flag
PSRZ
PSR zero (Z) flag
PSRn
PSR negative (N) flag
Seiko epson Corporation
Function
Description
Setting init. R/W
–
0x0 to 0x7 0x0
1 1 (enable) 0 0 (disable)
1 1 (set) 0 0 (cleared)
1 1 (set) 0 0 (cleared)
1 1 (set) 0 0 (cleared)
1 1 (set) 0 0 (cleared)
2 CPu
Remarks
– – 0 when being read.
R
0 R
0 R
0 R
0 R
0 R
2-5