Epson S1C17624 Technical Manual page 56

6 inTeRRuPT COnTROlleR (iTC)
note: The MISC_TTBRL and MISC_TTBRH registers are write-protected. Before these registers can
be rewritten, write protection must be removed by writing data 0x96 to the MISC_PROT register.
Note that since unnecessary rewrites to the MISC_TTBRL and MISC_TTBRH registers could lead
to erratic system operation, the MISC_PROT register should be set to other than 0x96 unless the
Vector Table Base Registers must be rewritten.
6.3 Control of Maskable interrupts
6.3.1 interrupt Control Bits in Peripheral Modules
The peripheral module that generates interrupts includes an interrupt enable bit and an interrupt flag for each inter-
rupt cause. The interrupt flag is set to 1 when the cause of interrupt occurs. By setting the interrupt enable bit to 1
(interrupt enabled), the flag state will be sent to the ITC as an interrupt request signal, generating an interrupt re-
quest to the S1C17 Core.
The corresponding interrupt enable bits should be set to 0 for those causes for which interrupts are not desired. In
this case, although the interrupt flag is set to 1 if the interrupt cause occurs, the interrupt request signal sent to the
ITC will not be asserted.
For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective pe-
ripheral module descriptions.
note: To prevent recurrence of the interrupt due to the same cause of interrupt, always reset the inter-
rupt flag in the peripheral module before enabling the interrupt, resetting the PSR, or executing
the reti instruction.
6.3.2 iTC interrupt Request Processing
On receiving an interrupt signal from a peripheral module, the ITC sends the interrupt request, interrupt level, and
vector number signals to the S1C17 Core.
Vector numbers are determined by the ITC internal hardware for each interrupt cause, as shown in Table 6.2.1.
The interrupt level is a value used by the S1C17 Core to compare with the IL bits (PSR). This interrupt level is used
in the S1C17 Core to disable subsequently occurring interrupts with the same or lower level. (See Section 6.3.3.)
The default ITC settings are level 0 for all maskable interrupts. Interrupt requests are not accepted by the S1C17
Core if the level is 0.
The ITC includes control bits for selecting the interrupt level, and the level can be set to between 0 (low) and 7 (high)
interrupt levels for each interrupt type.
If interrupt requests are input to the ITC simultaneously from two or more peripheral modules, the ITC outputs the
interrupt request with the highest priority to the S1C17 Core in accordance with the following conditions.
1. The interrupt with the highest interrupt level takes precedence.
2. If multiple interrupt requests are input with the same interrupt level, the interrupt with the lowest vector number
takes precedence.
The other interrupts occurring at the same time are held until all interrupts with higher priority levels have been ac-
cepted by the S1C17 Core.
If an interrupt cause with higher priority occurs while the ITC is outputting an interrupt request signal to the S1C17
Core (before being accepted by the S1C17 Core), the ITC alters the vector number and interrupt level signals to the
setting information on the more recent interrupt. The previously occurring interrupt is held. The held interrupt is
canceled and no interrupt is generated if the interrupt flag in the peripheral module is reset with software.
6-4
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S1C17624/604/622/602/621 TeChniCal Manual