Epson S1C17624 Technical Manual page 150

13.4.4 normal Clock Mode and half Clock Mode
T16A2 supports half clock mode to control the duty ratio of the PWM output waveform with high accuracy. In half
clock mode, T16A2 uses the dual-edge counter, which counts at the rising and falling edges of the count clock,
to compare with the compare A register. This makes it possible to control the duty ratio with double accuracy as
compared to normal clock mode.
Use HCM/T16A_CTLx register to select half clock mode.
normal clock mode (hCM = 0, default)
In normal clock mode, T16A2 generates a compare A signal when the T16A_TCx register value matches the
T16A_CCAx register.
half clock mode (hCM = 1)
In half clock mode, T16A2 generates a compare A signal when the dual-edge counter value matches the T16A_
CCAx register.
notes: • T16A2 must be placed into comparator mode to set half clock mode, as it is effective only
when PWM waveform is generated.
Be sure to set T16A2 to normal clock mode (HCM = 0) under a condition shown below.
(1) When T16A2 is placed into capture mode
(2) When TOUTAMD/T16A_CCCTLx register is set to 0x2 or 0x3
(3) When TOUTBMD/T16A_CCCTLx register is set to 0x2 or 0x3
• The dual-edge counter value cannot be read.
• Do not use the compare A interrupt in half clock mode.
13.5 Counter Control
13.5.1 Counter Reset
The counter can be reset to 0 by writing 1 to PRESET/T16A_CTLx register.
Normally, the counter should be reset by writing 1 to this bit before starting the count.
The counter is reset by the hardware if the counter reaches the compare B register value after the count starts.
note: Make sure the counter is halted (PRUN = 0) before setting PRESET.
13.5.2 Counter Run/STOP Control
Make the following settings before starting the count operation.
(1) Switch the input/output pin functions to be used for T16A2. See the "I/O Port (P)" chapter.
(2) Select operating modes. See Section 13.4.
(3) Select the clock source. See Section 13.3.
(4) Configure the timer outputs (TOUT). See Section 13.6.
(5) If using interrupts, set the interrupt level and enable the T16A2 interrupts. See Section 13.7.
(6) Reset the counter to 0. See Section 13.5.1.
(7) Set comparison data (in comparator mode). See Section 13.4.1.
Each timer channel provides PRUN/T16A_CTLx register to control the counter operation.
The counter starts counting when 1 is written to PRUN. Writing 0 to PRUN disables clock input and stops the
count.
This control does not affect the counter data. The counter data is retained even when the count is halted, allowing
resumption of the count from that data.
note: After the T16A_CCAx and T16A_CCBx registers have been set, wait for one or more T16A2 count
clock cycles and then run the counter.
S1C17624/604/622/602/621 TeChniCal Manual
Seiko epson Corporation
13 16-BiT PWM TiMeRS (T16a2)
13-7