Epson S1C17624 Technical Manual page 188

Stop bit
The stop bit length is selected by STPB/UART_MODx register. Setting STPB to 0 (default) configures the stop
bit length to 1 bit. Setting STPB to 1 configures it to 2 bits.
Parity bit
Whether the parity function is enabled or disabled is selected by PREN/UART_MODx register. Setting PREN
to 0 (default) disables the parity function. In this case, no parity bit is added to the transfer data and the data is
not checked for parity when received. Setting PREN to 1 enables the parity function. In this case, a parity bit is
added to the transfer data and the data is checked for parity when received. When the parity function is enabled,
the parity mode is selected by PMD/UART_MODx register. Setting PMD to 0 (default) adds a parity bit and
checks for even parity. Setting PMD to 1 adds a parity bit and checks for odd parity.
Sampling clock (sclk)
CHLN = 0, PREN = 0, STPB = 0
CHLN = 0, PREN = 1, STPB = 0
CHLN = 0, PREN = 0, STPB = 1
CHLN = 0, PREN = 1, STPB = 1
CHLN = 1, PREN = 0, STPB = 0
CHLN = 1, PREN = 1, STPB = 0
CHLN = 1, PREN = 0, STPB = 1
CHLN = 1, PREN = 1, STPB = 1
18.5 Data Transfer Control
Make the following settings before starting data transfers.
(1) Select the input clock. (See Section 18.3.)
Program T8F to output the transfer clock.
(2) Set the transfer data format. (See Section 18.4.)
(3) To use the IrDA interface, set IrDA mode. (See Section 18.8.)
(4) Set interrupt conditions to use UART interrupts. (See Section 18.7.)
note: Make sure the UART is halted (RXEN/UART_CTLx register = 0) before changing the above set-
tings.
enabling data transfers
Set RXEN/UART_CTLx register to 1 to enable data transfers. This puts the transmitter/receiver circuit in ready-
to-transmit/receive status.
note: Do not set RXEN to 0 while the UART is sending or receiving data.
Data transmission control
To start data transmission, write the transmit data to TXD[7:0]/UART_TXDx register.
The data is written to the transmit data buffer, and the transmitter circuit starts sending data.
The buffer data is sent to the transmit shift register, and the start bit is output from the SOUTx pin. The data in
the shift register is then output from the LSB. The transfer data bit is shifted in sync with the sampling clock
rising edge and output in sequence via the SOUTx pin. Following output of MSB, the parity bit (if parity is en-
abled) and the stop bit are output.
S1C17624/604/622/602/621 TeChniCal Manual
s1 D0 D1 D2 D3
s1 D0 D1 D2 D3
s1 D0 D1 D2 D3
s1 D0 D1 D2 D3
s1 D0 D1 D2 D3
s1 D0 D1 D2 D3
s1 D0 D1 D2 D3
s1 D0 D1 D2 D3
s1: start bit, s2 & s3: stop bit, p: parity bit
Figure 18.4.1 Transfer Data Format
Seiko epson Corporation
D4 D5 D6 s2
D4 D5 D6 p s2
D4 D5 D6 s2 s3
D4 D5 D6 p s2 s3
D4 D5 D6 D7 s2
D4 D5 D6 D7 p s2
D4 D5 D6 D7 s2 s3
D4 D5 D6 D7 p s2
18 uaRT
s3
18-3