Epson S1C17624 Technical Manual page 132

D10 CKaCTV: external Clock active level Select Bit
Selects the external input pulse polarity or external clock counting edge.
1 (R/W): Active high/rising edge (default)
0 (R/W): Active low/falling edge
This setting determines whether the external input clock rising edge or falling edge is used for counting
in external clock mode (when CKSL[1:0] = 0x1). In pulse width measurement mode (when CKSL[1:0]
= 0x2), this setting determines external input pulse polarity.
D[9:8] CKSl[1:0]: Operating Mode Select Bits
Selects the 16-bit timer operating mode.
Internal clock mode uses a divided PCLK clock as the count clock. The timer counts down from the ini-
tial value set in the reload data register and outputs an underflow signal when the counter underflows.
The underflow signal is used to generate an interrupt and an internal serial interface clock. The time un-
til underflow occurs can be finely programmed by selecting the clock division ratio and initial counter
value, making it useful for serial transfer clock generation and sporadic time measurement.
External clock mode uses the clock and pulses input via the EXCLx port as the count clock. This en-
ables T16 to be used as an event counter. Timer operations other than the input clock are the same as for
internal clock mode.
In pulse width measurement mode, when pulses with the specified polarity are input from the external
clock port, the internal clock is fed only while the input pulse is active, enabling counting. This enables
T16 to generate an interrupt when a pulse with the specified width or greater, or to measure the input
pulse width.
D[7:5] Reserved
D4 TRMD: Count Mode Select Bit
Selects the count mode.
1 (R/W): One-shot mode
0 (R/W): Repeat mode (default)
Setting TRMD to 0 sets the timer to repeat mode. In this mode, once the count starts, the timer contin-
ues to run until stopped by the application program. When the counter underflows, the timer presets the
counter to the reload data register value and continues the count. Thus, the timer periodically outputs an
underflow pulse. Set the timer to this mode to generate periodic interrupts or A/D conversion triggers at
desired intervals or to generate a serial transfer clock.
Setting TRMD to 1 sets the timer to one-shot mode. In this mode, the 16-bit timer stops automatically
as soon as the counter underflows. This means only one interrupt can be generated after the timer starts.
Note that the timer presets the counter to the reload data register value, then stops when an underflow
occurs. Set the timer to this mode to set a specific wait time or for pulse width measurement.
D[3:2] Reserved
D1 PReSeR: Timer Reset Bit
Resets the timer.
1 (W): Reset
0 (W): Ignored
0 (R): Always 0 when read (default)
Writing 1 to this bit presets the counter to the reload data value.
S1C17624/604/622/602/621 TeChniCal Manual
Table 11. 10.3 Operating Mode Selection
CKSl[1:0]
0x3
0x2 Pulse width measurement mode
0x1
0x0
Seiko epson Corporation
11 16-BiT TiMeRS (T16)
Operating mode
Reserved
External clock mode
Internal clock mode
(Default: 0x0)
11-9