Epson S1C17624 Technical Manual page 347

Register name address Bit
a/D Control/ 0x5384 D15
Status Register
(16 bits) D14–12 aDiCh[2:0] Conversion channel indicator
(aDC10_CTl)
D11
D10
D9
D8
D7–6 –
D5
D4
D3–2 –
D1
D0
a/D Clock 0x5386 D15–4 –
Control Register
(16 bits) D3–0 aDDF[3:0]
(aDC_DiV)
0x5067, 0x53a0–0x53ae
Register name address Bit
RFC Clock 0x5067 D7–4 –
Control Register D3–2 RFTCKDV
(8 bits)
(OSC_RFC)
D1
D0
RFC Control 0x53a0 D15–8 –
Register
(16 bits)
D7
(RFC_CTl)
D6
D5–4 SMODe[1:0] Sensor oscillation mode select
D3–2 –
D1
D0
RFC Oscillation 0x53a2 D15–3 –
Trigger Register
(16 bits)
D2
(RFC_TRG)
D1
D0
RFC 0x53a4 D15–0 MC[15:0]
Measurement (16 bits)
Counter low
Register
(RFC_MCl)
RFC 0x53a6 D15–8 –
Measurement
(16 bits) D7–0 MC[23:16]
Counter high
Register
(RFC_MCh)
RFC Time Base 0x53a8 D15–0 TC[15:0]
Counter low (16 bits)
Register
(RFC_TCl)
RFC Time Base 0x53aa D15–8 –
Counter high
(16 bits) D7–0 TC[23:16]
Register
(RFC_TCh)
S1C17624/604/622/602/621 TeChniCal Manual
name Function
– reserved
–
reserved
aDiBS ADC10 status
aDOWe
Overwrite error flag
aDCF
Conversion completion flag
reserved
aDOie Overwrite error interrupt enable
aDCie
Conversion completion int. enable 1 Enable
reserved
aDCTl
A/D conversion control
aDen
ADC10 enable
reserved
A/D converter clock division ratio
select
name Function
reserved
RFC clock division ratio select
[1:0]
RFTCKSRC RFC clock source select
RFTCKen RFC clock enable
reserved
COnen
Continuous oscillation enable
eVTen
Event counter mode enable
reserved
ChSel
Conversion channel select
RFCen RFC enable
reserved
SSenB
Sensor B oscillation control/status
SSena Sensor A oscillation control/status
SReF
Reference oscillation control/status 1 Start/Run
Measurement counter low-order
16-bit data
reserved
Measurement counter high-order
8-bit data
Time base counter low-order 16-
bit data
reserved
Time base counter high-order
8-bit data
Seiko epson Corporation
aPPenDiX a liST OF i/O ReGiSTeRS
Setting init. R/W
–
0x0 to 0x7 0x0
–
1 Busy 0 Idle
1 Error 0 Normal
1 Completed 0 Run/Stand-
by
–
1 Enable 0 Disable
0 Disable
–
1 Start 0 Stop
1 Enable 0 Disable
–
ADDF[3:0] Division ratio 0x0 R/W Source clock = PCLK
0xf reserved
0xe 1/32768
0xd 1/16384
0xc 1/8192
0xb 1/4096
0xa 1/2048
0x9 1/1024
0x8 1/512
0x7 1/256
0x6 1/128
0x5 1/64
0x4 1/32
0x3 1/16
0x2 1/8
0x1 1/4
0x0 1/2
Setting init. R/W
–
RFTCKDV[1:0] Division ratio 0x0 R/W When the clock
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
1 OSC1 0 HSCLK
1 Enable 0 Disable
–
1 Enable 0 Disable
1 Enable 0 Disable
SMODE[1:0] Sensor 0x0 R/W
0x3 reserved
0x2 DC capacitive
0x1 AC resistive
0x0 DC resistive
–
1 Ch.1 0 Ch.0
1 Enable 0 Disable
–
1 Start/Run 0 Stop
1 Start/Run 0 Stop
0 Stop
0x0–0xffff 0x0 R/W
–
0x0–0xff 0x0 R/W
0x0–0xffff 0x0 R/W
–
0x0–0xff 0x0 R/W
Remarks
– – 0 when being read.
R
– – 0 when being read.
0 R
0 R/W Reset by writing 1.
0 R Reset when ADC10_
ADD is read.
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
R/F Converter
Remarks
– – 0 when being read.
source is HSCLK
1 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W
0 R/W
– – 0 when being read.
– – 0 when being read.
aP-a-25