Epson S1C17624 Technical Manual page 71

7 ClOCK GeneRaTOR (ClG)
The IOSC clock is not supplied to the system immediately after IOSC oscillation starts until the time
set here has elapsed.
This is set to 64 cycles (IOSC clock) after an initial reset. This means the CPU can start operating when
the CPU operation start time at initial reset indicated below (at a maximum) has elapsed after the reset
state is canceled.
CPU operation start time at initial reset ≤ IOSC oscillation start time (max.) + IOSC oscilla-
tion stabilization wait time (64 cycles)
When the system clock is switched to IOSC immediately after turning the IOSC oscillator on, the IOSC
clock is supplied to the system after the IOSC clock system supply wait time indicated below (at a
maximum) has elapsed. If the power supply voltage V
be set to 0x3 to reduce the oscillation stabilization wait time.
IOSC clock system supply wait time ≤ IOSC oscillation start time (max.) + IOSC oscillation
stabilization wait time
D[5:4] OSC3WT[1:0]: OSC3 Wait Cycle Select Bits
An oscillation stabilization wait time is set to prevent malfunctions due to unstable clock operation at
the start of OSC3 oscillation.
The OSC3 clock is not supplied to the system immediately after OSC3 oscillation starts—e.g., when
the OSC3 oscillator is turned on with software—until the time set here has elapsed.
This is set to 1,024 cycles (OSC3 clock) after an initial reset.
When the system clock is switched to OSC3 immediately after the OSC3 oscillator circuit is turned on,
the OSC3 clock is supplied to the system after the OSC3 clock system supply wait time indicated below
(at a maximum) has elapsed.
OSC3 clock system supply wait time ≤ OSC3 oscillation start time (max.) + OSC3 oscilla-
tion
stabilization wait time
note: Oscillation stability will vary, depending on the resonator and other external components.
Carefully consider the OSC3 oscillation stabilization wait time before reducing the time.
D3 Reserved
D2 iOSCen: iOSC enable Bit
Enables or disables IOSC oscillator operations.
1 (R/W): Enabled (on) (default)
0 (R/W): Disabled (off)
note: The IOSC oscillator cannot be stopped if the IOSC clock is being used as the system clock.
7-12
Table 7. 9.3 IOSC Oscillation Stabilization Wait Time Settings
iOSCWT[1:0]
0x3
0x2
0x1
0x0
Table 7. 9.4 OSC3 Oscillation Stabilization Wait Time Settings
OSC3WT[1:0]
0x3
0x2
0x1
0x0
Seiko epson Corporation
Oscillation stabilization wait time
8 cycles
16 cycles
32 cycles
64 cycles
(Default: 0x0)
has stabilized sufficiently, IOSCWT[1:0] can
DD
Oscillation stabilization wait time
128 cycles
256 cycles
512 cycles
1024 cycles
(Default: 0x0)
S1C17624/604/622/602/621 TeChniCal Manual