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19 SPi
Pin name
i/O
SPICLK0 (Ch.0)
I/O
#SPISS0 (Ch.0)
I
note: Use an I/O (P) port to output the slave select signal when the SPI module is configured to master
mode.
The SPI input/output pins (SDIx, SDOx, SPICLKx, #SPISSx) are shared with I/O ports and are initially set as gen-
eral purpose I/O port pins. The pin functions must be switched using the port function select bits to use the general
purpose I/O port pins as SPI input/output pins.
For detailed information on pin function switching, see the "I/O Ports (P)" chapter.
19.3
SPi Clock
The master mode SPI uses the 16-bit timer (T16) Ch.1 output clock or a PCLK/4 clock to generate the SPI clock.
This clock is output from the SPICLKx pin to the slave device while also driving the shift register.
Use MCLK/SPI_CTLx register to select whether the T16 Ch.1 output clock or PCLK/4 clock is used.
Setting MCLK to 1 selects the T16 Ch.1 output clock; setting to 0 selects the PCLK/4 clock.
Using the T16 Ch.1 output clock enables programmable transfer rates. For more information on T16 control, see
the "16-bit Timers (T16)" chapter.
16-bit timer Ch.1 output clock
SPI clock (SPICLKx output)
In slave mode, the SPI clock is input via the SPICLKx pin.
19.4
Data Transfer Condition Settings
The SPI module can be set to master or slave modes. The SPI clock polarity/phase and bit direction (MSB first/LSB
first) can also be set via the SPI_CTLx register. The data length is fixed at 8 bits.
note: Make sure the SPI module is halted (SPEN/SPI_CTLx register = 0) before master/slave mode se-
lection and clock condition settings.
Master/slave mode selection
MSSL/SPI_CTLx register is used to set the SPI module to master mode or slave mode. Setting MSSL to 1 sets
master mode; setting it to 0 (default) sets slave mode. In master mode, data is transferred using the internal
clock. In slave mode, data is transferred by inputting the master device clock.
SPi clock polarity and phase settings
The SPI clock polarity is selected by CPOL/SPI_CTLx register. Setting CPOL to 1 treats the SPI clock as ac-
tive Low; setting it to 0 (default) treats it as active High.
The SPI clock phase is selected by CPHA/SPI_CTLx register.
As shown below, these control bits set transfer timing.
19-2
Qty
1
SPI external clock input/output pin
Outputs SPI clock when SPI is in master mode.
Inputs external clock when SPI is used in slave mode.
1
SPI slave select signal (active Low) input pin
SPI (Slave mode) is selected as a slave device by Low input to this pin.
PCLK
or
PCLK/4
Figure 19.
3.1 Master Mode SPI Clock
Seiko epson Corporation
Function
S1C17624/604/622/602/621 TeChniCal Manual
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