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This data length counter clock also uses a divided PCLK clock and can select one of 15 different types. The divi-
sion ratio to generate the data length counter clock is selected by LCCLK[3:0]/REMC_CFG register provided sepa-
rately to the carrier generation clock select bits.
Table 22.
lCClK[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
The data length counter can count up to 256. The count clock should be selected to ensure that the data length fits
within this range.
22.5
Data Transfer Control
Make the following settings before starting data transfers.
(1) Configure the carrier signal. (See Section 22.3.)
(2) Select the data length counter clock. (See Section 22.4.)
(3) Set the interrupt conditions. (See Section 22.6.)
note: Make sure the REMC module is halted (REMEN/REMC_CFG register = 0) before changing the
above settings.
Data transmission control
REMDT
REMO pin output
Carrier
REMDT
REMO pin output
Data length counter clock
REMLEN[7:0]
Interrupt signal
(1) Data transmit mode setting
Set REMC to transmit mode by writing 0 to REMMD/REMC_CFG register.
(2) Enabling data transmission
Enable REMC operation by setting REMEN/REMC_CFG register to 1. This initiates REMC transmission.
Set REMDT/REMC_LCNT register to 0 and REMLEN[7:0]/REMC_LCNT register to 0x0 before setting
REMEN to 1 to prevent unnecessary data transmission.
S1C17624/604/622/602/621 TeChniCal Manual
4.1 Data Length Counter Clock (PCLK Division Ratio) Selection
Division ratio
Reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
Figure 22.
5.1 Data Transmission
PCLK
4
Figure 22.
5.2 Underflow Interrupt Generation Timing
Seiko epson Corporation
22 iR ReMOTe COnTROlleR (ReMC)
lCClK[3:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
3
2
1
Division ratio
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)
0
22-3
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