Epson S1C17624 Technical Manual page 70

D1 hSClKSel: high-speed Clock Select Bit
Selects the high-speed clock (HSCLK).
1 (R/W): OSC3
0 (R/W): IOSC (default)
note: Both the IOSC and OSC3 oscillators must be active when selecting HSCLK. Otherwise,
HSCLK will not be switched, even when HSCLKSEL is written to, and the HSCLKSEL value
will remain unchanged.
D0 ClKSRC: System Clock Source Select Bit
Selects the system clock source.
1 (R/W): OSC1
0 (R/W): HSCLK (default)
HSCLK (IOSC or OSC3) is selected for normal (high-speed) operations. If the HSCLK clock is not
required, OSC1 can be set as the system clock and HSCLK (IOSC or OSC3) stopped to reduce current
consumption.
notes: • Both OSC1 and HSCLK must be operating when the system clock is selected (OSC1 or
HSCLK). Otherwise, the system will not switch system clocks, even when CLKSRC is written
to, and the CLKSRC value will remain unchanged. Furthermore, the system clock switching
operation takes a minimum one HSCLK cycle to maximum one OSC1 cycle. Table 7.9.2 lists
the combinations of clock operating states and register settings enabling system clock (OSC1
or HSCLK) selection.
iOSC
On
On
Off
• When switching the HSCLK source (IOSC↔OSC3), always make sure that PCKEN[1:0]/
CLG_PCLK register is set to 0x3 before writing to HSCLKSEL.
• The oscillator circuit selected as the system clock source cannot be turned off.
• Continuous write/read access to CLKSRC is prohibited. At least one instruction unrelated to
CLKSRC access must be inserted between the write and read instructions.
• Canceling HALT/SLEEP mode does not change the clock status configured before the chip
entered HALT/SLEEP mode.
Oscillation Control Register (OSC_CTl)
Register name address Bit
Oscillation 0x5061 D7–6 iOSCWT[1:0] IOSC wait cycle select
Control Register
(8 bits)
(OSC_CTl)
D5–4 OSC3WT[1:0] OSC3 wait cycle select
D3
D2
D1
D0
D[7:6] iOSCWT[1:0]: iOSC Wait Cycle Select Bits
An oscillation stabilization wait time is set to prevent malfunctions due to unstable clock operations at
the start of IOSC oscillation.
S1C17624/604/622/602/621 TeChniCal Manual
Table 7. 9.2 System Clock Switching (OSC1
OSC3 OSC1
On On
Off On
On On
name Function
– reserved
iOSCen
IOSC enable
OSC1en
OSC1 enable
OSC3en OSC3 enable
Seiko epson Corporation
7 ClOCK GeneRaTOR (ClG)
↔HSCLK) Conditions
hSClKSel System clock
*
IOSC/OSC3 or OSC1
0 IOSC or OSC1
1 OSC3 or OSC1
Setting
IOSCWT[1:0] Wait cycle
0x3 8 cycles
16 cycles
0x2
0x1 32 cycles
0x0 64 cycles
OSC3WT[1:0] Wait cycle
0x3 128 cycles
0x2 256 cycles
0x1 512 cycles
0x0 1024 cycles
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
init. R/W Remarks
0x0 R/W
0x0 R/W
– – 0 when being read.
1 R/W
0 R/W
0 R/W
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