Epson S1C17624 Technical Manual page 174

Cause of interrupt
32 Hz Interrupt
8 Hz Interrupt
2 Hz Interrupt
1 Hz Interrupt
For specific information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
notes: • The CT module interrupt flag must be reset in the interrupt handler routine after a CT interrupt
has occurred to prevent recurring interrupts.
• Reset the interrupt flag before enabling CT interrupts with the interrupt enable bit to prevent
occurrence of unwanted interrupt. The interrupt flag is reset by writing 1.
15.6 Control Register Details
address
0x5000 CT_CTL
0x5001 CT_CNT
0x5002 CT_IMSK
0x5003 CT_IFLG
The CT registers are described in detail below. These are 8-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
Clock Timer Control Register (CT_CTl)
Register name address Bit
Clock Timer 0x5000 D7–5 –
Control Register
(8 bits)
D4
(CT_CTl)
D3–1 –
D0
D[7:5] Reserved
D4 CTRST: Clock Timer Reset Bit
Resets the clock timer.
1 (W): Reset
0 (W): Ignored
0 (R): Always 0 when read (default)
Writing 1 to this bit resets the counter to 0x0. When reset in Run state, the clock timer restarts immedi-
ately after resetting. The reset data 0x0 is retained when in Stop state.
D[3:1] Reserved
D0 CTRun: Clock Timer Run/Stop Control Bit
Controls the clock timer Run/Stop.
1 (R/W): Run
0 (R/W): Stop (default)
The clock timer starts counting when CTRUN is written as 1 and stops when written as 0. The counter
data is retained at Stop state until a reset or the next Run state.
Clock Timer Counter Register (CT_CnT)
Register name address Bit
Clock Timer 0x5001 D7–0 CTCnT[7:0] Clock timer counter value
Counter Register
(8 bits)
(CT_CnT)
S1C17624/604/622/602/621 TeChniCal Manual
Table 15. 5.1 CT Interrupt Flags and Interrupt Enable Bits
interrupt flag
CTIF32/CT_IFLG register
CTIF8/CT_IFLG register
CTIF2/CT_IFLG register
CTIF1/CT_IFLG register
Table 15. 6.1 List of CT Registers
Register name
Clock Timer Control Register
Clock Timer Counter Register
Clock Timer Interrupt Mask Register
Clock Timer Interrupt Flag Register
name Function
reserved
CTRST
Clock timer reset
reserved
CTRun
Clock timer run/stop control
name Function
Seiko epson Corporation
interrupt enable bit
CTIE32/CT_IMSK register
CTIE8/CT_IMSK register
CTIE2/CT_IMSK register
CTIE1/CT_IMSK register
Function
Resets and starts/stops the timer.
Counter data
Enables/disables interrupt.
Indicates/resets interrupt occurrence status.
Setting init. R/W
–
1 Reset 0 Ignored
–
1 Run 0 Stop
Setting init. R/W
0x0 to 0xff 0x0
15 ClOCK TiMeR (CT)
Remarks
– – 0 when being read.
0 W
– –
0 R/W
Remarks
R
15-3