Epson S1C17624 Technical Manual page 302

28 MulTiPlieR/DiViDeR (COPRO)
Example:
ld.cw %r0,0x8 ; Sets the modes (unsigned division mode and 16 low-order bits output mode).
ld.ca %r0,%r1 ; Performs "res = %r0 ÷ %r1" and loads the 16 low-order bits of the result (quotient) to %r0.
ld.cw %r0,0x13 ; Sets the modes (operation result read mode and 16 high-order bits output mode).
ld.ca %r1,%r0 ; Loads the 16 high-order bits of the result (residue) to %r1.
28.5 MaC
The MAC (multiplication and accumulation) function performs "A (32 bits) = B (16 bits) × C (16 bits) + A (32
bits)."
Before performing a MAC operation, the initial value (A) must be set to the operation result register.
To clear the operation result register (A = 0), just set the operation mode to 0x0. It is not necessary to send 0x0 to
the multiplier/divider with another instruction.
To load a 16-bit value or a 32-bit value to the operation result register, set the operation mode to 0x1 (16 bits) or
0x2 (32 bits), respectively. Then send the initial value to the multiplier/divider using a "ld.cf" instruction.
Mode setting
instruction
value
0x0 –
0x1
ld.cf %rd,%rs
(ext
imm9)
ld.cf %rd,imm7
0x2 ld.cf %rd,%rs
(ext
imm9)
ld.cf %rd,imm7
To perform a MAC operation, set the operation mode to 0x7 (signed MAC). Then send the 16-bit multiplicand (B)
and 16-bit multiplier (C) to the multiplier/divider using a "ld.ca" instruction. The one-half (16 bits according
to the output mode) result (A[15:0] or A[31:16]) and the flag status will be returned to the CPU registers. Another
one-half should be read by setting the multiplier/divider into operation result read mode.
The overflow (V) flag in the PSR may be set to 1 according to the result. Other flags are set to 0.
When repeating the MAC operation without operation result read mode inserted, send multiplicand and multiplier
data for number of required times. In this case it is not necessary to set the MAC mode every time.
28-4
Argument 2
Argument 1
S1C17 Core
Coprocessor
output (16 bits)
Flag output
Figure 28. 5.1 Data Path in Initialize Mode
Table 28. 5.1 Initializing the Operation Result Register
Operations
res[31:0] ← 0x0
Setting the operating mode executes the initialization without
sending data.
res[31:16] ← 0x0
res[15:0] ← %rs
res[31:16] ← 0x0
res[15:0] ← imm7/16
res[31:16] ← %rd
res[15:0] ← %rs
res[31:16] ← %rd
res[15:0] ← imm7/16
Seiko epson Corporation
16 bits
32 bits
Operation result
register
Selector
Remarks
S1C17624/604/622/602/621 TeChniCal Manual
res: operation result register