Epson S1C17624 Technical Manual page 135

12 16-BiT PWM TiMeR (T16e)
12.2 T16e input/Output Pins
Table 12.2.1 lists the input/output pins for the T16E module.
Pin name
EXCL3 (Ch.0)
TOUT3 (Ch.0)
TOUTN3 (Ch.0)
The T16E output pins (TOUTx, and TOUTNx) are shared with I/O ports and are initially set as general purpose I/
O port pins. The pin functions must be switched using the port function select bits to use the general purpose I/O
port pins as T16E output pins. Also the T16E input pin (EXCLx) is shared with an I/O port. Setting the port to input
mode enables it to be used as the T16E input pin with a general-purpose input function. For detailed information on
pin function switching and port control, see the "I/O Ports (P)" chapter.
12.3 Operating Modes
The T16E module has the following two operating modes:
1. Internal clock mode (timer for counting an internal clock)
2. External clock mode (functions as an event counter)
The operating mode is selected using CLKSEL/T16E_CTLx register.
Setting CLKSEL to 0 (default) selects internal clock mode, while setting to 1 selects external clock mode.
12.3.1 internal Clock Mode
Internal clock mode uses a divided PCLK clock as the count clock.
The count clock is generated by dividing the PCLK clock into 1/1 to 1/16K. The division ratio can be selected from
the 15 types shown below using T16EDF[3:0]/T16E_DFx register.
T16eDF[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
notes: • The clock generator (CLG) must be configured to supply PCLK to the peripheral modules be-
fore running the timer.
• Make sure the counter is halted before setting the count clock.
For detailed information on the CLG control, see the "Clock Generator (CLG)" chapter.
12.3.2 external Clock Mode
External clock mode uses the clock and pulses input via the EXCLx port as the count clock. This enables T16E to
be used as an event counter. Timer operations other than the input clock are the same as for internal clock mode.
To input an external clock to T16E, the I/O port shared with an EXCLx input must be set to input mode in advance. For
detailed information on the port control, see the "I/O Ports (P)" chapter.
The T16E counter counts up at the rising edge of the input signal.
12-2
Table 12. 2.1 List of T16E Pins
i/O Qty
I 1 External clock input pin
Inputs an external clock for the event counter function.
O 1 Non-inverted PWM signal output pin
Outputs the PWM signal generated by the timer.
O 1 Inverted PWM signal output pin
Outputs the inverted PWM signal generated by the timer.
Table 12. 3.1.1 PCLK Division Ratio Selection
Division ratio
Reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
Seiko epson Corporation
Function
T16eDF[3:0] Division ratio
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
S1C17624/604/622/602/621 TeChniCal Manual
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)