I2Cm: Transmit Data Specifying Slave Address And Transfer Direction - Epson S1C17624 Technical Manual

The start condition is generated by setting STRT/I2CM_CTL register to 1.
STRT is automatically reset to 0 once the start condition is generated. The I
(2) Slave address transmission
Once the start condition has been generated, the I
and transfer direction for communications. I
8-bit transfer data register to send the slave address and transfer direction bit, enabling single transfers in 7-bit
address mode. In 10-bit mode, data is sent twice or three times under software control. Figure 20.5.2 shows the
configuration of the address data.
7-bit address
10-bit address
First transmit data
Second transmit data
(When receiving data)
Issue a repeated start condition after the second data has been sent and then send the third data as shown below.
Third transmit data
Figure 20.
The transfer direction bit indicates the data transfer direction after the slave address has been sent. This is set to
0 when sending data from the master to the slave and to 1 when receiving data from the slave. To send a slave
address, set the address with the transfer direction bit to RTDT[7:0]/I2CM_DAT register. At the same time, set
TXE/I2CM_DAT register transmitting the address to 1.
After the slave address has been output, data can be sent and received as many times as required. Data must be
sent or received according to the transfer direction set together with the slave address.
Data transmission control
The procedure for transmitting data is described below. Data transmission is performed by the same procedure
as for slave address transmission.
To send byte data, set the transmit data to RTDT[7:0] and set TXE to 1 to transmit 1 byte.
When TXE is set to 1, the I2CM module begins data transmission in sync with the clock. If the previous data
is currently being transmitted, data transmission starts after this has been completed. The I2CM module first
transfers the data written to the shift register, then starts outputting the clock from the SCL0 pin. TXE is reset to
0 at this point and a cause of interrupt occurs, enabling the subsequent transmission data and TXE to be set.
The data bits in the shift register are shifted in sequence at the clock falling edge and output via the SDA0 pin
with the MSB leading. The I2CM module outputs 9 clocks with each data transmission. In the 9th clock cycle,
the I2CM module sets the SDA line into high impedance to receive an ACK or NAK sent from the slave device.
S1C17624/604/622/602/621 TeChniCal Manual
SDA0 (output)
SCL0 (output)
Start condition
Figure 20. 5.1 Start Condition
2 C master (this module) sends a bit indicating the slave address
C slave addresses are either 7-bit or 10-bit. This module uses an
2
D7 D6 D5 D4 D3
A6 A5 A4 A3 A2
Slave address
D7 D6 D5 D4 D3
1 1 1 1 0
2 high order
slave address bits
D7 D6 D5 D4 D3
A7 A6 A5 A4 A3
8 low order slave address bits
D7 D6 D5 D4 D3
1 1 1 1 0
2 high order
slave address bits
5.2 Transmit Data Specifying Slave Address and Transfer Direction
Seiko epson Corporation
2 C bus is busy from this point on.
D2 D1 D0
A1 A0 DIR
Transfer direction
0: master → slave (transmission)
1: slave → master (reception)
D2 D1 D0
A9 A8 0
D2 D1 D0
A2 A1 A0
D2 D1 D0
A9 A8 1
2
20 i C MaSTeR (i2CM)
20-3