Epson S1C17624 Technical Manual page 131

11 16-BiT TiMeRS (T16)
D[3:0] DF[3:0]: Count Clock Division Ratio Select Bits
Selects a PCLK division ratio to generate the count clock.
DF[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
note: Make sure the counter is halted before setting the count clock.
T16 Ch.x Reload Data Registers (T16_TRx)
Register name address Bit
T16 Ch.x 0x4222 D15–0 TR[15:0]
Reload Data 0x4242
Register 0x4262
(T16_TRx)
(16 bits)
D[15:0] TR[15:0]: Reload Data Bits
Sets the counter initial value. (Default: 0x0)
The reload data set in this register is preset to the counter when the timer is reset or the counter under-
flows. If the timer is started after resetting, it counts down from the reload value (initial value). This
means that the reload value and the input clock frequency determine the time elapsed from the point at
which the timer starts until the underflow occurs (or between underflows). The time determined is used
to obtain the desired wait time, the intervals between periodic interrupts or A/D conversion trigger, and
the programmable serial interface transfer clock.
T16 Ch.x Counter Data Registers (T16_TCx)
Register name address Bit
T16 Ch.x 0x4224 D15–0 TC[15:0]
Counter Data 0x4244
Register 0x4264
(T16_TCx)
(16 bits)
D[15:0] TC[15:0]: Counter Data Bits
The counter data can be read out. (Default: 0xffff)
This register is read-only and cannot be written to.
T16 Ch.x Control Registers (T16_CTlx)
Register name address Bit
T16 Ch.x 0x4226 D15–11 –
Control Register 0x4246
D10
(T16_CTlx) 0x4266
D9–8 CKSl[1:0]
(16 bits)
D7–5 –
D4
D3–2 –
D1
D0
D[15:11] Reserved
11-8
Table 11. 10.2 PCLK Division Ratio Selection
Division ratio
Reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
name Function
Reload data
TR15 = MSB
TR0 = LSB
name Function
Counter data
TC15 = MSB
TC0 = LSB
name Function
reserved
CKaCTV External clock active level select
Operating mode select
reserved
TRMD
Count mode select
reserved
PReSeR
Timer reset
PRun
Timer run/stop control
Seiko epson Corporation
DF[3:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Setting init. R/W
0x0 to 0xffff 0x0 R/W
Setting init. R/W
0x0 to 0xffff 0xffff
Setting init. R/W
–
1 High 0 Low
CKSL[1:0] Mode 0x0 R/W
0x3 reserved
0x2 Pulse width
0x1 External clock
0x0 Internal clock
–
1 One shot 0 Repeat
–
1 Reset 0 Ignored
1 Run 0 Stop
S1C17624/604/622/602/621 TeChniCal Manual
Division ratio
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)
Remarks
Remarks
R
Remarks
– – 0 when being read.
1 R/W
– – 0 when being read.
0 R/W
– – 0 when being read.
0 W
0 R/W