Epson S1C17624 Technical Manual page 175

15 ClOCK TiMeR (CT)
D[7:0] CTCnT[7:0]: Clock Timer Counter Value
The counter data can be read out. (Default: 0x0)
This register is read-only and cannot be written to.
The bits correspond to various frequencies, as follows:
D7: 1 Hz, D6: 2 Hz, D5: 4 Hz, D4: 8 Hz, D3: 16 Hz, D2: 32 Hz, D1: 64 Hz, D0: 128 Hz
note: The correct counter value may not be read out (reading is unstable) if the register is read while
counting is underway. Read the counter register twice in succession and treat the value as valid if
the values read are identical.
Clock Timer interrupt Mask Register (CT_iMSK)
Register name address Bit
Clock Timer 0x5002 D7–4 –
interrupt Mask (8 bits)
D3
Register
D2
(CT_iMSK)
D1
D0
This register enables or disables interrupt requests individually for the 32 Hz, 8 Hz, 2 Hz, and 1 Hz signals. Setting
CTIE* to 1 enables CT interrupts for the corresponding frequency signal falling edge, while setting to 0 disables
interrupts.
D[7:4] Reserved
D3 CTie32: 32 hz interrupt enable Bit
Enables or disables 32 Hz interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D2 CTie8: 8 hz interrupt enable Bit
Enables or disables 8 Hz interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D1 CTie2: 2 hz interrupt enable Bit
Enables or disables 2 Hz interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D0 CTie1: 1 hz interrupt enable Bit
Enables or disables 1 Hz interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Clock Timer interrupt Flag Register (CT_iFlG)
Register name address Bit
Clock Timer 0x5003 D7–4 –
interrupt Flag
(8 bits)
D3
Register
D2
(CT_iFlG)
D1
D0
This register indicates the occurrence state of interrupt causes due to 32 Hz, 8 Hz, 2 Hz, and 1 Hz signals. If a CT
interrupt occurs, identify the interrupt cause (frequency) by reading the interrupt flag in this register. CTIF* is a CT
module interrupt flag that is set to 1 at the falling edge of the corresponding 32 Hz, 8 Hz, 2 Hz, or 1 Hz interrupt.
CTIF* is reset by writing 1.
D[7:4] Reserved
15-4
name Function
reserved
CTie32 32 Hz interrupt enable
CTie8
8 Hz interrupt enable
CTie2
2 Hz interrupt enable
CTie1 1 Hz interrupt enable
name Function
reserved
CTiF32
32 Hz interrupt flag
CTiF8 8 Hz interrupt flag
CTiF2
2 Hz interrupt flag
CTiF1
1 Hz interrupt flag
Seiko epson Corporation
Setting init. R/W
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
Setting init. R/W
–
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
Remarks
– – 0 when being read.
0 R/W Reset by writing 1.
0 R/W
0 R/W
0 R/W