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27 On-ChiP DeBuGGeR (DBG)
D1
Se: Single Step enable Bit
Enables or disables single-step operations.
1 (R/W): Enabled
0 (R/W): Disabled (default)
D0
DM: Debug Mode Bit
Indicates the processor operating mode (debug mode or user mode).
1 (R):
Debug mode
0 (R):
User mode (default)
instruction Break address Register 2 (iBaR2)
Register name address
Bit
instruction
0xffffb8
D31–24 –
Break address
(32 bits)
D23–0 iBaR2[23:0] Instruction break address #2
Register 2
(iBaR2)
D[31:24] Reserved
D[23:0]
iBaR2[23:0]: instruction Break address #2 Bits
Sets instruction break address #2. (Default: 0x000000)
instruction Break address Register 3 (iBaR3)
Register name address
Bit
instruction
0xffffbc
D31–24 –
Break address
(32 bits)
D23–0 iBaR3[23:0] Instruction break address #3
Register 3
(iBaR3)
D[31:24] Reserved
D[23:0]
iBaR3[23:0]: instruction Break address #3 Bits
Sets instruction break address #3. (Default: 0x000000)
instruction Break address Register 4 (iBaR4)
Register name address
Bit
instruction
0xffffd0
D31–24 –
Break address
(32 bits)
D23–0 iBaR4[23:0] Instruction break address #4
Register 4
(iBaR4)
D[31:24] Reserved
D[23:0]
iBaR4[23:0]: instruction Break address #4 Bits
Sets instruction break address #4. (Default: 0x000000)
27-6
name
Function
reserved
IBAR223 = MSB
IBAR20 = LSB
name
Function
reserved
IBAR323 = MSB
IBAR30 = LSB
name
Function
reserved
IBAR423 = MSB
IBAR40 = LSB
Seiko epson Corporation
Setting
init. R/W
–
–
–
0x0 to 0xffffff
0x0 R/W
Setting
init. R/W
–
–
–
0x0 to 0xffffff
0x0 R/W
Setting
init. R/W
–
–
–
0x0 to 0xffffff
0x0 R/W
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
0 when being read.
Remarks
0 when being read.
Remarks
0 when being read.
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