Epson S1C17624 Technical Manual page 269

24 a/D COnVeRTeR (aDC10)
Conversion completion interrupt
To use this interrupt, set ADCIE/ADC10_CTL register to 1. If ADCIE is set to 0 (default), interrupt requests for
this cause will not be sent to the ITC.
When A/D conversion in a channel has completed, the A/D converter sets ADCF/ADC10_CTL register to 1,
indicating that the converted data can be read out. If conversion completion interrupts are enabled (ADCIE = 1),
an interrupt request is sent simultaneously to the ITC.
An interrupt occurs if other interrupt conditions are met.
You can inspect ADCF in the ADC10 interrupt handler routine to determine whether the ADC10 interrupt is
attributable to a completion of conversion. If ADCF is 1, the converted data can be read out from ADD[15:0]/
ADC10_ADD register by the interrupt handler routine. The interrupt cause ADCF is reset to 0 by reading
ADD[15:0] and this interrupt will not be generated until the subsequent conversion has completed.
Conversion data overwrite error interrupt
To use this interrupt, set ADOIE/ADC10_CTL register to 1. If ADOIE is set to 0 (default), interrupt requests
for this cause will not be sent to the ITC.
If the following A/D conversion has completed when ADD[15:0] has not been read (ADCF = 1), the A/D con-
verter sets ADOWE/ADC10_CTL register to 1, indicating that ADD[15:0] is overwritten. If conversion data
overwrite error interrupts are enabled (ADOIE = 1), an interrupt request is sent simultaneously to the ITC.
An interrupt occurs if other interrupt conditions are met.
You can inspect ADOWE in the ADC10 interrupt handler routine to determine whether the ADC10 interrupt is
attributable to an overwrite error. If ADOWE is 1, perform error handling by the interrupt handler routine. The
interrupt cause ADOWE is reset to 0 by writing 1.
For more information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
notes: • To prevent interrupt recurrences, the ADCF/ADC10_CTL register and ADOWE/ADC10_CTL
register must be reset in the interrupt handler routine after an ADC10 interrupt has occurred.
• To prevent unwanted interrupts, reset ADCF and ADOWE before enabling interrupts with AD-
CIE/ADC10_CTL register and ADOIE/ADC10_CTL register.
24.6 Control Register Details
address
0x5380 ADC10_ADD
0x5382 ADC10_TRG
0x5384 ADC10_CTL
0x5386 ADC_DIV
The A/D converter registers are described in detail below. These are 16-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
a/D Conversion Result Register (aDC10_aDD)
Register name address Bit
a/D Conversion 0x5380 D15–0 aDD[15:0]
Result Register (16 bits)
(aDC10_aDD)
D[15:0] aDD[15:0]: a/D Converted Data Bits
The A/D conversion results are stored. (Default: 0x0)
The data alignment in this 16-bit register (conversion result storing mode) can be selected using the
STMD/ADC10_TRG register.
24-8
Table 24. 6.1 List of ADC10 Registers
Register name
A/D Conversion Result Register
A/D Trigger/Channel Select Register
A/D Control/Status Register
A/D Clock Control Register
name Function
A/D converted data
ADD[9:0] are effective when
STMD = 0 (ADD[15:10] = 0)
ADD[15:6] are effective when
STMD = 1 (ADD[5:0] = 0)
Seiko epson Corporation
Function
A/D converted data
Sets start/end channels and conversion mode.
Controls A/D converter and indicates conversion status.
Controls A/D converter clock.
Setting init. R/W
0x0 to 0x3ff 0x0
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
R