Epson S1C17624 Technical Manual page 155

13 16-BiT PWM TiMeRS (T16a2)
notes: • Reset the interrupt flag before enabling interrupts with the interrupt enable bit to prevent oc-
currence of unwanted interrupt. The interrupt flag is reset by writing 1.
• After an interrupt occurs, the interrupt flag in the T16A2 module must be reset in the interrupt
handler routine.
13.8 Control Register Details
address
0x5068 T16A_CLK0
0x5069 T16A_CLK1
0x5400 T16A_CTL0
0x5402 T16A_TC0
0x5404 T16A_CCCTL0 T16A Comparator/Capture Ch.0 Control Register
0x5406 T16A_CCA0
0x5408 T16A_CCB0
0x540a T16A_IEN0
0x540c T16A_IFLG0
0x5420 T16A_CTL1
0x5422 T16A_TC1
0x5424 T16A_CCCTL1 T16A Comparator/Capture Ch.1 Control Register
0x5426 T16A_CCA1
0x5428 T16A_CCB1
0x542a T16A_IEN1
0x542c T16A_IFLG1
The T16A2 registers are described in detail below.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
T16a Clock Control Register Ch.x (T16a_ClKx)
Register name address Bit
T16a Clock 0x5068 D7–4 ClKDiV
Control Register 0x5069
Ch.x
(8 bits)
(T16a_ClKx)
D3–2 ClKSRC
D1
D0
D[7:4] ClKDiV[3:0]: Clock Division Ratio Select Bits
Selects the division ratio for generating the count clock when an internal clock (IOSC, OSC3, or OSC1)
is used.
13-12
Table 13. 8.1 List of T16A2 Registers
Register name
T16A Clock Control Register Ch.0
T16A Clock Control Register Ch.1
T16A Counter Ch.0 Control Register
T16A Counter Ch.0 Data Register
T16A Compare/Capture Ch.0 A Data Register
T16A Compare/Capture Ch.0 B Data Register
T16A Compare/Capture Ch.0 Interrupt Enable Register Enables/disables interrupts.
T16A Compare/Capture Ch.0 Interrupt Flag Register
T16A Counter Ch.1 Control Register
T16A Counter Ch.1 Data Register
T16A Compare/Capture Ch.1 A Data Register
T16A Compare/Capture Ch.1 B Data Register
T16A Compare/Capture Ch.1 Interrupt Enable Register Enables/disables interrupts.
T16A Compare/Capture Ch.1 Interrupt Flag Register
name Function
Clock division ratio select
[3:0]
Clock source select
[1:0]
MulTiMD Multi-comparator/capture mode
select
–
reserved
ClKen
Count clock enable
Seiko epson Corporation
Function
Controls the T16A2 Ch.0 clock.
Controls the T16A2 Ch.1 clock.
Controls the counter.
Counter data
Controls the comparator/capture block and TOUT.
Compare A/capture A data
Compare B/capture B data
Displays/sets interrupt occurrence status.
Controls the counter.
Counter data
Controls the comparator/capture block and TOUT.
Compare A/capture A data
Compare B/capture B data
Displays/sets interrupt occurrence status.
Setting init. R/W
Division ratio 0x0 R/W
CLKDIV[3:0]
OSC3 or OSC1
IOSC
0xf – –
0xe 1/16384 –
0xd 1/8192 –
0xc 1/4096 –
0xb 1/2048 –
0xa 1/1024 –
0x9 1/512 –
0x8 1/256 1/256
0x7 1/128 1/128
0x6 1/64 1/64
0x5 1/32 1/32
0x4 1/16 1/16
0x3 1/8 1/8
0x2 1/4 1/4
0x1 1/2 1/2
0x0 1/1 1/1
CLKSRC[1:0] Clock source 0x0 R/W
0x3 External clock
0x2 OSC3
0x1 OSC1
0x0 IOSC
1 Multi 0 Normal
–
1 Enable 0 Disable
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
0 R/W T16A_CLK0
– – T16A_CLK1
0 when being read.
0 R/W