Epson S1C17624 Technical Manual page 173

15 ClOCK TiMeR (CT)
The clock timer starts operating when 1 is written to CTRUN. Writing 0 to CTRUN disables clock input and stops
the operation.
This control does not affect the counter (CT_CNT register) data. The counter data is retained even when the count
is halted, allowing resumption of the count from that data.
If 1 is written to both CTRUN and CTRST simultaneously, the clock timer starts counting after resetting.
A cause of interrupt occurs during counting at the 32 Hz, 8 Hz, 2 Hz, and 1 Hz signal falling edges. If interrupts are
enabled, an interrupt request is sent to the interrupt controller (ITC).
OSC1/128 256 Hz
CTCNT0 128 Hz
CTCNT1 64 Hz
CTCNT2 32 Hz
CTCNT3 16 Hz
CTCNT4 8 Hz
CTCNT5 4 Hz
CTCNT6 2 Hz
CTCNT7 1 Hz
32 Hz interrupt
8 Hz interrupt
2 Hz interrupt
1 Hz interrupt
notes: • The clock timer switches to Run/Stop status synchronized with the 256 Hz signal falling edge
after data is written to CTRUN. When 0 is written to CTRUN, the timer stops after counting an
additional "+1." 1 is retained for CTRUN reading until the timer actually stops.
Figure 15.4.2 shows the Run/Stop control timing chart.
• Executing the slp instruction while the timer is running (CTRUN = 1) will destabilize the timer
operation during restarting from SLEEP status. When switching to SLEEP status, stop the
timer (CTRUN = 0) before executing the slp instruction.
15.5 CT interrupts
The CT module includes functions for generating the following four kinds of interrupts:
32 Hz, 8 Hz, 2 Hz, and 1 Hz interrupts
The CT module outputs a single interrupt signal shared by the above four interrupt causes to the interrupt controller
(ITC). The interrupt flag in the CT module should be read to identify the cause of interrupt that occurred.
32 hz, 8 hz, 2 hz, and 1 hz interrupts
The 32 Hz, 8 Hz, 2 Hz, and 1 Hz signal falling edges set the corresponding interrupt flag in the CT module to 1.
At the same time, an interrupt request is sent to the ITC if the corresponding interrupt enable bit has been set to
1 (interrupt enabled). An interrupt is generated if the ITC and S1C17 Core interrupt conditions are satisfied.
If the interrupt enable bit is set to 0 (interrupt disabled, default), no interrupt request will be sent to the ITC.
15-2
Figure 15. 4.1 Clock Timer Timing Chart
256 Hz
CTRUN(RD)
CTRUN(WR)
CT_CNT register 0x57
Figure 15. 4.2 Run/Stop Control Timing Chart
Seiko epson Corporation
0x58 0x59 0x5a 0x5b 0x5c
S1C17624/604/622/602/621 TeChniCal Manual