Epson S1C17624 Technical Manual page 363

Revision History
Code no. Page
411914900 All New establishment
411914901 Second Notice
cover (Old) No description
(New) This product uses SuperFlash
1-1 Features: Clock generator - Other
(Old) • IOSC control for quick-restart processing from SLEEP mode
(New) Deleted
1-8, 1-11 Pad configuration diagram: Chip (S1C17604/S1C17622)
Modified Figures 1.3.2.2 and 1.3.3.2
7-1 CLG: CLG module overview
(Old) • Supports quick-restart processing from SLEEP mode.
(New) Deleted
CLG: CLG module configuration
Modified Figure 7.1.1
7-7, 7-11 CLG: System clock switching
(Old) • When SLEEP mode is canceled, the IOSC oscillator circuit is turned on (IOSCEN = 1) and is ...
(New) • Canceling HALT/SLEEP mode does not change the clock status configured before the chip en-
7-8 CLG: Peripheral module clock control circuit
Modified Figure 7.6.1 and Table 7.6.2
CLG: Peripheral module clock (PCLK) control
(Old) No description
(New) Note: The interrupt controller (ITC) needs PCLK only when the register is set.
7-9 CLG: FOUTH/FOUT1 output
Modified Figures 7.7.2 and 7.7.3
7-14, 7-15 CLG: PCLK Control Register (CLG_PCLK)
(Old) No description
(New) Peripheral modules that use PCLK ...
9-5, 9-11 P: I/O port chattering filter function
(Old) No description
(New) Notes: • An unexpected interrupt may occur ... disabled before placing the CPU into SLEEP status.
10-4 T8F: T8F output signals
(Old) No description
(New) Use the following equations to calculate the reload data register value ...
12-6 T16E: Precautions on fine mode
(Old) No description
(New) (3) When fine mode is used, set compare data with B < A / 2 + 0x8000.
13-6 T16A2: One-shot mode (TRMD = 1)
(Old) No description
(New) The counter is not cleared to 0 after the count operation is completed in one-shot mode. ...
13-7 T16A2: Counter RUN/STOP control
(Old) No description
(New) Note: After the T16A_CCAx and T16A_CCBx registers ... and then run the counter.
13-8 T16A2: Operation timing in capture mode
Modified Figure 13.5.4.2
13-18 T16A2: T16A Comparator/Capture Ch.x A/B Data Registers (T16A_CCAx/CCBx)
(Old) No description
(New) Note: After the T16A_CCAx/CCBx registers ... and then run the counter.
Turns IOSC on forcibly and switches the system clock to IOSC when SLEEP mode is canceled.
Canceling HALT mode does not change the clock status configured before the chip entered HALT
mode.
tered HALT/SLEEP mode.
• Interrupt controller (ITC) ...
Notes: • ...
• The interrupt controller (ITC) needs PCLK only when the register is set.
TFMD: Fine mode setting (0 to 15)
For more information on resetting methods, see Section 13.5.1, "Counter Reset."
In capture mode (CCAMD = 1)/(CCBMD = 1)
When the counter value is captured at the external trigger signal (CAPAx/CAPBx) edge selected ...
thus the captured counter value can be read out in the interrupt handler.
Contents
® technology licensed from Silicon Storage Technology, Inc.
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