Epson S1C17624 Technical Manual page 86

8 Real-TiMe ClOCK (RTC)
Writing 1 to this bit causes the RTC to operate as follows:
• When the 10-second counter is 3 or more, the RTC generates a carry over of 1 to start counting by
the 1-minute counter.
• When the 10-second counter is 2 or less, the RTC does not generate a carry over of 1.
After being set to 1, this bit remains set for the 4-ms period needed for the processing above, then is au-
tomatically reset to 0.
note: Accessing the counters while RTCADJ = 1 is prohibited. Writing 0 to this bit during such time
is also prohibited, because it would cause the RTC to operate erratically.
D1 RTCSTP: Divider Run/Stop Control Bit
This bit starts or stops the divider. It also indicates divider operating status.
1 (R/W): Stop divider/counters
0 (R/W): Start divider/counters (software reset value)
Setting this bit to 0 starts the divider; setting it to 1 stops the divider. The value read from this bit is 0
when the divider/counters are operating, and 1 when the counters are idle.
This bit starts/stops the divider at the 32-kHz input clock divide-by stage of 8,192 Hz or stages that fol-
low. The counters do not stop at up to the input clock divide-by-2 stage (16,384 Hz).
If the divider stops while carry of a counter is taking place, the count value may be corrupted. There-
fore, see Section 8.3.5 to ensure that carry is not taking place when the divider is stopped. This is not
required when, for example, the contents of all counters are newly set again.
D0 RTCRST: Software Reset Bit
This bit resets the divider and output signals.
1 (R/W): Reset
0 (R/W): Negate reset (software reset value)
To perform software reset, write 1 to RTCRST and then write 0.
The software reset clears the 32 kHz to 2 Hz divider bits, negates the interrupt request signal, and ini-
tializes some control bits.
When setting up the RTC, first perform software reset using RTCRST.
RTC Control 1 Register (RTC_CnTl1)
Register name address Bit
RTC Control 1 0x5143 D7–3 –
Register
(8 bits)
D2
(RTC_CnTl1)
D1
D0
Init.: ( ) indicates the value set after a software reset (RTCRST → 1 → 0) is performed.
D[7:3] Reserved
D2 RTCRDhlD: Read Buffer enable Bit
This bit enables or disables the read buffer.
1 (R/W): Enabled
0 (R/W): Disabled (software reset value)
In order to prevent carry over during reading counters, the RTC includes a read buffer to hold counter
data. Before reading counter data, set RTCRDHLD to 1 to load the current counter data to the read buf-
fer. While RTCRDHLD is set to 1, the buffered data is read out from the counter registers. Be sure to
reset RTCRDHLD to 0 after the buffered data is read out. This operation does not affect the counters.
The counters keeps counting while RTCRDHLD is set to 1.
D1 RTCBSY: Counter Busy Flag Bit
This flag indicates whether 1 is being carried over to the next-digit counter.
1 (R): Busy (while carry is taking place)
0 (R): Accessible for read/write (software reset value)
8-12
name Function
reserved
RTCRDhlD Read buffer enable
RTCBSY Counter busy flag
RTChlD Counter hold control
Seiko epson Corporation
Setting init. R/W
–
1 Enable 0 Disable X (0) R/W
1 Busy 0 R/W possible X (0)
1 Hold 0 Running X (0) R/W
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
– – 0 when being read.
R