Epson S1C17624 Technical Manual page 193

18 uaRT
Table 18.
note: This clock must be selected as a clock faster than sclk16.
The demodulator circuit treats Low pulses with a width of at least two IrDA receive detection clock
cycles as valid and converts them to 16 × sclk16 cycle width Low pulses. Select a clock to enable
detection of input pulses with a minimum width of 1.41 µs.
Serial data transfer control
Data transfer control in IrDA mode is identical to that for normal interfaces. For detailed information on data
format settings and data transfer and interrupt control methods, refer to the preceding sections.
18.9 Control Register Details
address
0x4100 UART_ST0 UART Ch.0 Status Register
0x4101 UART_TXD0 UART Ch.0 Transmit Data Register
0x4102 UART_RXD0 UART Ch.0 Receive Data Register
0x4103 UART_MOD0 UART Ch.0 Mode Register
0x4104 UART_CTL0 UART Ch.0 Control Register
0x4105 UART_EXP0 UART Ch.0 Expansion Register
0x4120 UART_ST1 UART Ch.1 Status Register
0x4121 UART_TXD1 UART Ch.1 Transmit Data Register
0x4122 UART_RXD1 UART Ch.1 Receive Data Register
0x4123 UART_MOD1 UART Ch.1 Mode Register
0x4124 UART_CTL1 UART Ch.1 Control Register
0x4125 UART_EXP1 UART Ch.1 Expansion Register
The UART registers are described in detail below. These are 8-bit registers.
notes: • When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
• The following UART bits should be set with transfers disabled (RXEN = 0).
- All UART_MODx register bits (STPB, PMD, PREN, CHLN)
- RBFI bit in the UART_CTLx register
- All UART_EXPx register bits (IRMD, IRCLK[2:0])
uaRT Ch.x Status Registers (uaRT_STx)
Register name address Bit
uaRT Ch.x 0x4100
D7
Status Register 0x4120
D6
(uaRT_STx)
(8 bits)
D5
D4
D3
D2
D1
D0
D7 Reserved
18-8
8.1 IrDA Receive Detection Clock (PCLK Division Ratio) Selection
iRClK[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Table 18. 9.1 List of UART Registers
Register name
name Function
–
reserved
FeR Framing error flag
PeR
Parity error flag
OeR
Overrun error flag
RD2B Second byte receive flag
TRBS
Transmit busy flag
RDRY
Receive data ready flag
TDBe Transmit data buffer empty flag
Seiko epson Corporation
Division ratio
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)
Function
Indicates transfer, buffer and error statuses.
Transmit data
Receive data
Sets transfer data format.
Controls data transfer.
Sets IrDA mode.
Indicates transfer, buffer and error statuses.
Transmit data
Receive data
Sets transfer data format.
Controls data transfer.
Sets IrDA mode.
Setting
–
1 Error 0 Normal
1 Error 0 Normal
1 Error 0 Normal
1 Ready 0 Empty
1 Busy 0 Idle
1 Ready 0 Empty
1 Empty 0 Not empty
S1C17624/604/622/602/621 TeChniCal Manual
init. R/W Remarks
– – 0 when being read.
0 R/W Reset by writing 1.
0 R/W
0 R/W
0 R
0 R Shift register status
0 R
1 R