Epson S1C17624 Technical Manual page 122

10 Fine MODe 8-BiT TiMeRS (T8F)
Underflow signal (not corrected)
Underflow signal (corrected)
Output clock (not corrected)
Output clock (corrected)
D[7:5] Reserved
D4 TRMD: Count Mode Select Bit
Selects the count mode.
1 (R/W): One-shot mode
0 (R/W): Repeat mode (default)
Setting TRMD to 0 sets the timer to repeat mode. In this mode, once the count starts, the timer contin-
ues to run until stopped by the application program. When the counter underflows, the timer presets the
counter to the reload data register value and continues the count. Thus, the timer periodically outputs an
underflow pulse. Set the timer to this mode to generate periodic interrupts or to generate a serial trans-
fer clock.
Setting TRMD to 1 sets the timer to one-shot mode. In this mode, the fine mode 8-bit timer stops auto-
matically as soon as the counter underflows. This means only one interrupt can be generated after the
timer starts. Note that the timer presets the counter to the reload data register value, then stops when an
underflow occurs. Set the timer to this mode to set a specific wait time.
D[3:2] Reserved
D1 PReSeR: Timer Reset Bit
Resets the timer.
1 (W): Reset
0 (W): Ignored
0 (R): Always 0 when read (default)
Writing 1 to this bit presets the counter to the reload data value.
D0 PRun: Timer Run/Stop Control Bit
Controls the timer RUN/STOP.
1 (R/W): Run
0 (R/W): Stop (default)
The timer starts counting when PRUN is written as 1 and stops when written as 0. When the timer is
stopped, the counter data is retained until reset or until the next RUN state.
T8F Ch.x interrupt Control Registers (T8F_inTx)
Register name address Bit
T8F Ch.x inter- 0x4208 D15–9 –
rupt Control 0x4288
D8
Register
(16 bits)
D7–1 –
(T8F_inTx)
D0
D[15:9] Reserved
D8 T8Fie: T8F interrupt enable Bit
Enables or disables interrupts caused by counter underflows for each channel.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting T8FIE to 1 enables T8F interrupt requests to the ITC; setting to 0 disables interrupts.
10-8
Count clock
15
15
Figure 10. 10.1 Delay Cycle Insertion in Fine Mode
name Function
reserved
T8Fie T8F interrupt enable
reserved
T8FiF
T8F interrupt flag
Seiko epson Corporation
16
16
Delayed
Setting init. R/W
–
1 Enable 0 Disable
–
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
S1C17624/604/622/602/621 TeChniCal Manual
1
1
Remarks
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W Reset by writing 1.