Epson S1C17624 Technical Manual page 95

notes: • An unexpected interrupt may occur after SLEEP status is canceled if the slp instruction is
executed while the chattering filter function is enabled. The chattering filter must be disabled
before placing the CPU into SLEEP status.
• The chattering filter check time refers to the maximum pulse width that can be filtered.
Generating an input interrupt requires a minimum input time of the check time and a maximum
input time of twice the check time.
• The Px port interrupt must be disabled before setting the Px_CHAT register. Setting the regis-
ter while the interrupt is enabled may generate inadvertent Px port interrupt. Also the chatter-
ing filter circuit requires a maximum of twice the check time for stabilizing the operation status.
Before enabling the interrupt, make sure that the stabilization time has elapsed.
9.7 Port input interrupt
Chattering filter
Px0 PxCF1[2:0]
Interrupt edge selection
PxEDGE0
Interrupt enable
PxIE0
Px7 PxCF2[2:0]
PxEDGE7
PxIE7
The P0 and P1 ports include input interrupt functions.
Select which of the 16 ports are to be used for interrupts based on requirements. You can also select whether inter-
rupts are generated for either the rising edge or falling edge of the input signals.
interrupt port selection
Select the port generating an interrupt using PxIEy/Px_IMSK register.
Setting PxIEy to 1 enables interrupt generation by the corresponding port. Setting to 0 (default) disables inter-
rupt generation.
interrupt edge selection
Port input interrupts can be generated at either the rising edge or falling edge of the input signal. Select the edge
used to generate interrupts using PxEDGEy/Px_EDGE register.
Setting PxEDGEy to 1 generates port input interrupts at the input signal falling edge. Setting it to 0 (default)
generates interrupts at the rising edge.
S1C17624/604/622/602/621 TeChniCal Manual
Table 9. 6.1 Chattering Filter Function Settings
PxCF1[2:0]/PxCF2[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Figure 9. 7.1 Port Input Interrupt Circuit Configuration
Seiko epson Corporation
Check time *
16384/f (8 ms)
PCLK
8192/f (4 ms)
PCLK
4096/f (2 ms)
PCLK
2048/f (1 ms)
PCLK
1024/f (512 µs)
PCLK
512/f (256 µs)
PCLK
256/f (128 µs)
PCLK
No check time (off)
(Default: 0x0, * when PCLK = 2 MHz)
Interrupt flag
PxIF0
PxIF7
9 i/O PORTS (P)
Px port
interrupt request
(to ITC)
(Px = P0 and P1)
9-5