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Operating mode
Flash erase/
programming
mode 1
For the DSPC[1:0] settings, see "LCD Display Control Register (LCD_DCTL)" in the "LCD Driver (LCD)"
chapter.
4.5
heavy load Protection Function
In order to ensure a stable circuit behavior and LCD display quality even if the power supply voltage fluctuates due
to driving an external load, the internal logic voltage regulator and the LCD system voltage regulator have a heavy
load protection function.
The internal logic voltage regulator enters heavy load protection mode by writing 1 to the HVLD/VD1_CTL regis-
ter and it ensures stable V
V
may become unstable in the operations shown below and in other conditions. If the IC operations are unstable
D1
due to these conditions during evaluation, set the internal logic voltage regulator to heavy load protection mode be-
fore starting the operations.
• When driving a diode or buzzer in which a large current flows using a port output (Maintain the regulator in
heavy load protection mode while the port is driving the load.)
• When switching the system clock from the high-speed clock to the low-speed clock and vice versa (Set the regu-
lator in heavy load protection mode immediately before switching the clock and maintain it for several 10 µs
after the switching has completed.)
• When turning the high-speed oscillator (OSC3, IOSC) on (Set the regulator in heavy load protection mode im-
mediately before turning the oscillator on and maintain it until the oscillation stabilization wait time has elapsed.)
• When placing/releasing the system into/from HALT/SLEEP mode at frequent intervals (Maintain the regulator in
heavy load protection mode while the processing is being repeated.)
The LCD system voltage regulator enters heavy load protection mode by writing 1 to the LHVLD/LCD_VREG
register and it ensures stable V
inconsistencies in density.
note: Current consumption increases in heavy load protection mode, therefore do not set heavy load
protection mode with software if unnecessary.
4.6
Control Register Details
address
0x5120
VD1_CTL
0x50a3
LCD_VREG
The power control registers are described in detail below. These are all 8-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
V
Control Register (VD1_CTl)
D1
Register name address
Bit
V
Control
0x5120
D7–6 –
D1
Register
(8 bits)
D5
(VD1_CTl)
D4–1 –
D0
D[7:6]
Reserved
S1C17624/604/622/602/621 TeChniCal Manual
Condition
V
lCD driver
DD
1.8 to 2.7 V
2.7 to 3.6 V
Not used
output.
D1
–V
outputs. Use the heavy load protection function when the LCD display has
C1
C3
Table 4.
6.1 List of Power Control Registers
Register name
V
Control Register
D1
LCD Voltage Regulator Control Register
name
Function
reserved
hVlD
V
heavy load protection mode
D1
reserved
VD1MD
Flash erase/programming mode
Seiko epson Corporation
Control bits
VD1MD
VCSel
–
(Not supported)
Used
1
1
Controls the V
Controls the LCD drive voltage regulator.
Setting
–
1 On
–
1 Flash (2.5 V) 0 Norm.(1.8 V)
4 POWeR SuPPlY
DSPC[1:0]
1
Other than 0x0
0
0x0
Function
voltage and heavy load protection mode.
D1
init. R/W
–
–
0 when being read.
0 Off
0
R/W
–
–
0 when being read.
0
R/W
Remarks
4-3
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