Epson S1C17624 Technical Manual page 237

22 iR ReMOTe COnTROlleR (ReMC)
(3) Transmission data setting
Set the data to be transmitted (High or Low) to REMDT/REMC_LCNT register.
Setting REMDT to 1 outputs High; setting it to 0 outputs Low from the REMO pin after being modulated by
the carrier signal.
(4) Data pulse length setting
Set the value corresponding to the data pulse length (High or Low section) to REMLEN[7:0]/REMC_LCNT
register to set to the data length counter.
Given below is the value to which the data length counter is set:
Setting value = Data pulse length (seconds) × Data length counter clock frequency (Hz)
The data length counter starts counting down from the value written using the data length counter clock selected.
A cause of underflow interrupt occurs when the data length counter value reaches 0. If the interrupt is enabled,
an REMC interrupt request is output to the interrupt controller (ITC). The data length counter stops counting at
the same time with the counter value 0 maintained.
(5) Interrupt handling
To transmit the subsequent data, set the subsequent data (Step 3) and set the data pulse length (Step 4) in the
interrupt handler routine executed by the data length counter underflow.
(6) Terminating data transmission
To terminate data transmission, set REMEN to 0 after the final data transmission has completed (after an under-
flow interrupt has occurred).
Data reception control
PCLK
Data length counter clock
REMI input
REMDT
(Sampled waveform)
REMRIF
REMFIF
Interrupt signal
REMLEN[7:0]
(1) Data receive mode setting
Set REMC to receive mode by writing 1 to REMMD/REMC_CFG register.
(2) Enabling data reception
Enable REMC operation by setting REMEN/REMC_CFG register to 1. This initiates REMC reception (input
edge detection).
REMC detects an input transition (signal rising or falling edges) by sampling the input signal from the REMI
pin using the carrier generation clock. If a signal edge is detected, a cause of rising or falling edge interrupt is
generated. An REMC interrupt request is output to the ITC if the interrupt is enabled. Rising edge and falling
edge interrupts can be individually enabled or disabled.
Note that if the signal level after the input has changed is not detected for at least two continuous sampling
clock cycles, the input signal transition is interpreted as noise, and no rising or falling edge interrupt is gener-
ated.
22-4
x+2 x+1 x
Figure 22. 5.3 Data Reception
Seiko epson Corporation
Write 1
0xff 0xfe 0xfd
Write 0xff
S1C17624/604/622/602/621 TeChniCal Manual
Write 1
0xff
Write 0xff