Epson S1C17624 Technical Manual page 168

14.9 T8OSC1 interrupts
The T8OSC1 module outputs an interrupt request to the interrupt controller (ITC) by compare match.
Compare match interrupt
This interrupt request is generated when the counter matches the compare data register value during counting. It
sets the interrupt flag T8OIF/T8OSC1_IFLG register in the T8OSC1 module to 1.
To use this interrupt, set T8OIE/T8OSC1_IMSK register to 1. If T8OIE is set to 0 (default), T8OIE is not set to 1,
and an interrupt request for this cause is not sent to the ITC.
If T8OIF is set to 1, the T8OSC1 module outputs an interrupt request to the ITC. An interrupt is generated if the ITC
and S1C17 core interrupt conditions are satisfied.
For more information on interrupt control registers and the operation when an interrupt occurs, see the "Interrupt
Controller (ITC)" chapter.
notes: • To prevent interrupt recurrences, the T8OSC1 module interrupt flag T8OIF must be reset in
the interrupt handler routine following a T8OSC1 interrupt.
• To prevent generating unnecessary interrupts, reset T8OIF before enabling T8OSC1 interrupts
using T8OIE.
14.10 Control Register Details
address
0x5065 OSC_T8OSC1
0x50c0 T8OSC1_CTL
0x50c1 T8OSC1_CNT
0x50c2 T8OSC1_CMP
0x50c3 T8OSC1_IMSK T8OSC1 Interrupt Mask Register
0x50c4 T8OSC1_IFLG
0x50c5 T8OSC1_DUTY T8OSC1 PWM Duty Data Register
The T8OSC1 registers are described in detail below. These are 8-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
T8OSC1 Clock Control Register (OSC_T8OSC1)
Register name address Bit
T8OSC1 Clock 0x5065 D7–4 –
Control Register (8 bits) D3–1 T8O1CK
(OSC_T8OSC1)
D0
D[7:4] Reserved
D[3:1] T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits
Selects the division ratio for generating the count clock.
S1C17624/604/622/602/621 TeChniCal Manual
Table 14. 10.1 List of T8OSC1 Registers
Register name
T8OSC1 Clock Control Register
T8OSC1 Control Register
T8OSC1 Counter Data Register
T8OSC1 Compare Data Register
T8OSC1 Interrupt Flag Register
name Function
reserved
T8OSC1 clock division ratio select T8O1CK[2:0]
[2:0]
T8O1Ce
Clock enable
Seiko epson Corporation
14 8-BiT OSC1 TiMeR (T8OSC1)
Function
Controls the count clock.
Sets the timer mode and starts/stops the timer.
Counter data
Sets compare data.
Sets the interrupt mask.
Indicates and reset interrupt occurrence status.
Sets data for PWM output.
Setting init. R/W
–
Division ratio 0x0 R/W Clock source: OSC1
0x7–0x6 reserved
0x5 1/32
0x4 1/16
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
1 Enable 0 Disable
Remarks
– – 0 when being read.
0 R/W
14-5