Epson S1C17624 Technical Manual page 57

hardware interrupt
P0 port interrupt
P1 port interrupt
Stopwatch timer (SWT) interrupt
Clock timer (CT) interrupt /
Real-time clock (RTC) interrupt (S1C17624/604)
8-bit OSC1 timer (T8OSC1) interrupt
Supply voltage detector (SVD) interrupt
LCD driver (LCD) interrupt /
16-bit PWM timer (T16A2) Ch.0 interrupt (S1C17624/604)
16-bit PWM timer (T16E) Ch.0 interrupt
8-bit timer (T8F) Ch.0 & Ch.1 interrupt
16-bit timer (T16) Ch.0 interrupt
16-bit timer (T16) Ch.1 interrupt
16-bit timer (T16) Ch.2 interrupt
UART Ch.0 interrupt
2
I C slave (I2CS) interrupt /
UART Ch.1 interrupt
SPI Ch.0 interrupt
2
I C master (I2CM) interrupt
IR remote controller (REMC) interrupt
16-bit PWM timer (T16A2) Ch.1 interrupt (S1C17624/604) ILV17[2:0] (D[10:8]/ITC_LV8 register)
A/D converter (ADC10) interrupt
R/F converter (RFC) interrupt
6.3.3 interrupt Processing by the S1C17 Core
A maskable interrupt to the S1C17 Core occurs when all of the following conditions are met:
• The interrupt is enabled by the interrupt control bit inside the peripheral module.
• The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core has been set to 1.
• The cause of interrupt that has occurred has a higher interrupt level than the value set in the IL field of the PSR.
• No other cause of interrupt having higher priority, such as NMI, has occurred.
If an interrupt cause that has been enabled in the peripheral module occurs, the corresponding interrupt flag is set to 1,
and this state is maintained until it is reset by the program. This means that the interrupt cause is not cleared even if
the conditions listed above are not met when the interrupt cause occurs. An interrupt occurs if the above conditions
are met.
If multiple maskable interrupt causes occurs simultaneously, the interrupt cause with the highest interrupt level and
lowest vector number becomes the subject of the interrupt request to the S1C17 Core. Interrupts with lower levels
are held until the above conditions are subsequently met.
The S1C17 Core samples interrupt requests for each cycle. On accepting an interrupt request, the S1C17 Core
switches to interrupt processing immediately after execution of the current instruction has been completed.
Interrupt processing involves the following steps:
(1) The PSR and current program counter (PC) values are saved to the stack.
(2) The PSR IE bit is reset to 0 (disabling subsequent maskable interrupts).
(3) The PSR IL bits are set to the received interrupt level. (The NMI does not affect the IL bits.)
(4) The vector for the interrupt occurred is loaded to the PC to execute the interrupt handler routine.
When an interrupt is accepted, (2) prevents subsequent maskable interrupts. Setting the IE bit to 1 in the interrupt
handler routine allows handling of multiple interrupts. In this case, since IL is changed by (3), only an interrupt
with a higher level than that of the currently processed interrupt will be accepted.
Ending interrupt handler routines using the reti instruction returns the PSR to the state before the interrupt has
occurred. The program resumes processing following the instruction being executed at the time the interrupt oc-
curred.
S1C17624/604/622/602/621 TeChniCal Manual
Table 6. 3.2.1 Interrupt Level Setting Bits
ILV0[2:0] (D[2:0]/ITC_LV0 register)
ILV1[2:0] (D[10:8]/ITC_LV0 register)
ILV2[2:0] (D[2:0]/ITC_LV1 register)
ILV3[2:0] (D[10:8]/ITC_LV1 register)
ILV4[2:0] (D[2:0]/ITC_LV2 register)
ILV5[2:0] (D[10:8]/ITC_LV2 register)
ILV6[2:0] (D[2:0]/ITC_LV3 register)
ILV7[2:0] (D[10:8]/ITC_LV3 register)
ILV8[2:0] (D[2:0]/ITC_LV4 register)
ILV9[2:0] (D[10:8]/ITC_LV4 register)
ILV10[2:0] (D[2:0]/ITC_LV5 register)
ILV11[2:0] (D[10:8]/ITC_LV5 register)
ILV12[2:0] (D[2:0]/ITC_LV6 register)
ILV13[2:0] (D[10:8]/ITC_LV6 register)
ILV14[2:0] (D[2:0]/ITC_LV7 register)
ILV15[2:0] (D[10:8]/ITC_LV7 register)
ILV16[2:0] (D[2:0]/ITC_LV8 register)
ILV18[2:0] (D[2:0]/ITC_LV9 register)
ILV19[2:0] (D[10:8]/ITC_LV9 register)
Seiko epson Corporation
6 inTeRRuPT COnTROlleR (iTC)
interrupt level setting bits Register address
0x4306
0x4306
0x4308
0x4308
0x430a
0x430a
0x430c
0x430c
0x430e
0x430e
0x4310
0x4310
0x4312
0x4312
0x4314
0x4314
0x4316
0x4316
0x4318
0x4318
6-5