Epson S1C17624 Technical Manual page 289

26 SuPPlY VOlTaGe DeTeCTOR (SVD)
26.3 Comparison Voltage Setting
The SVD circuit compares the power supply voltage (V
puts results indicating whether the power supply voltage exceeds this comparison voltage. The comparison voltage
can be selected from among the 15 levels listed in Table 26.3.1 with the SVDC[3:0]/SVD_CMP register.
26.4 SVD Control
Power supply voltage detection using the SVD circuit is initiated by writing 1 to SVDEN/SVD_EN register and is
stopped by writing 0.
The results can be read out from the SVDDT/SVD_RSLT register.
The detection results and SVDDT readings are as follows.
• When power supply voltage (V
• When power supply voltage (V
When SVD interrupts are enabled and SVDEN is set to 1, an interrupt occurs as soon as the power supply voltage
drops below the comparison voltage, and the detection result becomes 1. This interrupt can be used to indicate bat-
tery depletion and to initiate the heavy load protection function. See the following section for more information on
interrupt control.
Note that if a temporary voltage drop causes an interrupt, the interrupt will not be cleared even when the voltage
subsequently returns to a value exceeding the comparison voltage. The SVDDT should be checked in the interrupt
handler routine.
notes: • An SVD circuit-enable response time is required to obtain stable detection results after
SVDEN is altered from 0 to 1. Also when SVDC[3:0] is altered, an SVD circuit response time
is required to obtain stable detection results. For these response times, see "Electrical Char-
acteristics."
• Operating the SVD circuit increases current consumption. If power supply voltage detection is
not required, stop SVD operations by setting SVDEN to 0.
26.5 SVD interrupt
The SVD module includes a function for generating interrupts when power supply voltage drops are detected.
Power supply voltage drop detection interrupt
This cause of interrupt is generated when the power supply voltage (V
parison voltage while SVD is operating (SVDEN = 1). It sets the interrupt flag SVDIF/SVD_IFLG register in
the SVD module to 1. Once set, SVDIF is not reset even if the power supply voltage subsequently returns to a
value exceeding the comparison voltage. SVDIF is reset to 0 by writing 1.
26-2
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Table 26. 3.1 Comparison Voltage Settings
SVDC[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
) ≥ comparison voltage: SVDDT = 0
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) < comparison voltage: SVDDT = 1
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Seiko epson Corporation
) against the comparison voltage set by software and out-
Comparison voltage
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
2.0 V
1.9 V
1.8 V
Reserved
(Default: 0x0)
) detected value drops below the com-
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S1C17624/604/622/602/621 TeChniCal Manual