Epson S1C17624 Technical Manual page 334

aPPenDiX a liST OF i/O ReGiSTeRS
Register name address Bit
Stopwatch 0x5021 D7–4 BCD10[3:0] 1/10 sec. BCD counter value
Timer BCD
(8 bits)
Counter Register D3–0 BCD100[3:0] 1/100 sec. BCD counter value
(SWT_BCnT)
Stopwatch 0x5022 D7–3 –
Timer interrupt
(8 bits)
D2
Mask Register
D1
(SWT_iMSK)
D0
Stopwatch 0x5023 D7–3 –
Timer interrupt
(8 bits)
D2
Flag Register
D1
(SWT_iFlG)
D0
0x5040–0x5041
Register name address Bit
Watchdog 0x5040 D7–5 –
Timer Control
(8 bits)
D4
Register
D3–0 WDTRun[3:0] Watchdog timer run/stop control
(WDT_CTl)
Watchdog 0x5041 D7–2 –
Timer Status (8 bits)
Register
D1
(WDT_ST)
D0
0x5060–0x5081
Register name address Bit
Clock Source 0x5060 D7–2 –
Select Register (8 bits)
D1
(OSC_SRC)
D0
Oscillation 0x5061 D7–6 iOSCWT[1:0] IOSC wait cycle select
Control Register (8 bits)
(OSC_CTl)
D5–4 OSC3WT[1:0] OSC3 wait cycle select
D3
D2
D1
D0
noise Filter 0x5062 D7–2 –
enable Register (8 bits)
D1
(OSC_nFen)
D0
FOuT Control 0x5064 D7–4 –
Register (8 bits)
D3–2 FOuThD
(OSC_FOuT)
D1
D0
PClK Control 0x5080 D7–2 –
Register
(8 bits) D1–0 PCKen[1:0] PCLK enable
(ClG_PClK)
CClK Control 0x5081 D7–2 –
Register
(8 bits) D1–0 CClKGR[1:0] CCLK clock gear ratio select
(ClG_CClK)
aP-a-12
name Function
reserved
Sie1
1 Hz interrupt enable
Sie10
10 Hz interrupt enable
Sie100 100 Hz interrupt enable
reserved
SiF1
1 Hz interrupt flag
SiF10 10 Hz interrupt flag
SiF100
100 Hz interrupt flag
name Function
reserved
WDTRST
Watchdog timer reset
reserved
WDTMD
NMI/Reset mode select
WDTST NMI status
name Function
reserved
hSClKSel High-speed clock select
ClKSRC System clock source select
–
reserved
iOSCen IOSC enable
OSC1en
OSC1 enable
OSC3en
OSC3 enable
reserved
RSTFe Reset noise filter enable
nMiFe
NMI noise filter enable
reserved
FOUTH clock division ratio select
[1:0]
FOuThe FOUTH output enable
FOuT1e
FOUT1 output enable
reserved
reserved
Seiko epson Corporation
Setting init. R/W
0 to 9
0 to 9
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
–
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
Setting init. R/W
–
1 Reset 0 Ignored
Other than 1010 1010 1010 R/W
Run Stop
–
1 Reset 0 NMI
1 NMI occurred 0 Not occurred
Setting init. R/W
–
1 OSC3 0 IOSC
1 OSC1 0 HSCLK
IOSCWT[1:0] Wait cycle 0x0 R/W
0x3 8 cycles
0x2 16 cycles
0x1 32 cycles
0x0 64 cycles
OSC3WT[1:0] Wait cycle 0x0 R/W
0x3 128 cycles
0x2 256 cycles
0x1 512 cycles
0x0 1024 cycles
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
–
1 Enable 0 Disable
1 Enable 0 Disable
–
FOUTHD[1:0] Division ratio 0x0 R/W Source clock =
0x3 reserved
0x2 1/4
0x1 1/2
0x0 1/1
1 Enable 0 Disable
1 Enable 0 Disable
–
PCKEN[1:0] PCLK supply 0x3 R/W
0x3 Enable
0x2 Not allowed
0x1 Not allowed
0x0 Disable
–
CCLKGR[1:0] Gear ratio 0x0 R/W
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
0 R
0 R
– – 0 when being read.
0 R/W
0 R/W
0 R/W
– – 0 when being read.
0 R/W Reset by writing 1.
0 R/W
0 R/W
Watchdog Timer
Remarks
– – 0 when being read.
0 W
– – 0 when being read.
0 R/W
0 R
Clock Generator
Remarks
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
1 R/W
0 R/W
0 R/W
– – 0 when being read.
1 R/W
0 R/W
– – 0 when being read.
HSCLK
0 R/W
0 R/W
– – 0 when being read.
– – 0 when being read.