Epson S1C17624 Technical Manual page 101

Px Port Chattering Filter Control Registers (Px_ChaT)
Register name address Bit
Px Port 0x5208
D7
Chattering 0x5218
D6–4 PxCF2[2:0] Px[7:4] chattering filter time select
Filter Control (8 bits)
Register
(Px_ChaT)
D3
D2–0 PxCF1[2:0] Px[3:0] chattering filter time select
note: The PxCHAT registers are available only for P0 and P1 ports.
D7 Reserved
D[6:4] PxCF2[2:0]: Px[7:4] Chattering Filter Time Select Bits
Configures the chattering filter circuit for the Px[7:4] ports.
D3 Reserved
D[2:0] PxCF1[2:0]: Px[3:0] Chattering Filter Time Select Bits
Configures the chattering filter circuit for the Px[3:0] ports.
The P0 and P1 ports include a chattering filter circuit for key entry that can be disabled or enabled
with a check time specified individually for the four Px[3:0] and Px[7:4] ports using PxCF1[2:0] and
PxCF2[2:0], respectively.
notes: • An unexpected interrupt may occur after SLEEP status is canceled if the slp instruction is
executed while the chattering filter function is enabled. The chattering filter must be disabled
before placing the CPU into SLEEP status.
• The chattering filter check time refers to the maximum pulse width that can be filtered. Gen-
erating an input interrupt requires a minimum input time of the check time and a maximum
input time of twice the check time.
• The Px port interrupt must be disabled before setting the Px_CHAT register. Setting the reg-
ister while the interrupt is enabled may generate inadvertent Px interrupt. Also the chattering
filter circuit requires a maximum of twice the check time for stabilizing the operation status.
Before enabling the interrupt, make sure that the stabilization time has elapsed.
S1C17624/604/622/602/621 TeChniCal Manual
name Function
–
reserved
–
reserved
Table 9. 9.2 Chattering Filter Function Settings
PxCF1[2:0]/PxCF2[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko epson Corporation
Setting
–
PxCF2[2:0] Filter time
0x7 16384/f
0x6 8192/f
0x5 4096/f
0x4 2048/f
0x3 1024/f
0x2 512/f
0x1 256/f
0x0 None
–
PxCF1[2:0] Filter time
0x7 16384/f
0x6 8192/f
0x5 4096/f
0x4 2048/f
0x3 1024/f
0x2 512/f
0x1 256/f
0x0 None
Check time *
16384/f (8 ms)
PCLK
8192/f (4 ms)
PCLK
4096/f (2 ms)
PCLK
2048/f (1 ms)
PCLK
1024/f (512 µs)
PCLK
512/f (256 µs)
PCLK
256/f (128 µs)
PCLK
No check time (off)
(Default: 0x0, * when PCLK = 2 MHz)
9 i/O PORTS (P)
init. R/W Remarks
– – 0 when being read.
0x0 R/W
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
– – 0 when being read.
0x0 R/W
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
9-11