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28 MulTiPlieR/DiViDeR (COPRO)
28.6
Reading Operation Results
The "ld.ca" instruction cannot load a 32-bit operation result to a CPU register, so a multiplication or MAC opera-
tion returns the one-half (16 bits according to the output mode) result (A[15:0] or A[31:16]) and the flag status to
the CPU registers. Another one-half should be read by setting the multiplier/divider into operation result read mode.
The operation result register keeps the loaded operation result until it is rewritten by other operation.
Mode setting
instruction
value
0x03
ld.ca %rd,%rs
ld.ca %rd,imm7 %rd ← res[15:0]
0x13
ld.ca %rd,%rs
ld.ca %rd,imm7 %rd ← res[31:16]
28-6
Argument 2
Argument 1
S1C17 Core
Coprocessor
output (16 bits)
Flag output
Figure 28.
6.1 Data Path in Operation Result Read Mode
Table 28.
6.1 Operation in Operation Result Read Mode
Operations
%rd ← res[15:0]
%rd ← res[31:16]
Seiko epson Corporation
Operation result
register
Selector
Flags
psr (CVZN) ← 0b0000 This operation mode does not
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
affect the operation result reg-
ister.
res: operation result register
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