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19 SPi
note: When the SPI module is used in master mode with CPHA set to 0, the clock may change a mini-
mum of one system clock (PCLK) cycle time from change of the first transmit data bit.
16-bit timer output
SPI_TXDx register
Figure 19.
The half SPICLKx cycle will be secured from change of data to change of the clock for the second
and following transmit data bits and the second and following bytes during continuous transfer.
Data reception control
In master mode, write dummy data to SPTDB[7:0]/SPI_TXDx register. Writing to the SPI_TXDx register cre-
ates the trigger for reception as well as transmission start. Writing actual transmit data enables simultaneous
transmission and reception.
This starts the SPI clock output from the SPICLKx pin.
In slave mode, the module waits until the clock is input from the SPICLKx pin. There is no need to write to the
SPI_TXDx register if no transmission is required. The receiving operation is started by the clock input from the
master device. If data is transmitted simultaneously, write transmit data to the SPI_TXDx register before the
clock is input.
The data is received in sequence in the shift register at the rising or falling edge of the clock determined by
CPHA/SPI_CTLx register and CPOL/SPI_CTLx register. (See Figure 19.4.1.) The received data is loaded into
the receive data buffer once the 8 bits of data are received in the shift register.
The received data in the buffer can be read from SPRDB[7:0]/SPI_RXDx register.
The SPI module includes SPRBF/SPI_STx register for reception control.
The SPRBF flag indicates the receive data buffer status. This flag is set to 1 when the data received in the shift
register is loaded into the receive data buffer, indicating that the received data can be read out. It reverts to 0
when the buffer data is read out from the SPI_RXDx register. An interrupt can be generated as soon as the flag
is set to 1 (see Section 19.6). The received data should be read out either by using this interrupt or by inspecting
the SPRBF flag to confirm that the receive data buffer contains valid received data. The receive data buffer is 1
byte in size, but a shift register is also provided, enabling received data to be retained in the buffer even while
the subsequent data is being received. Note that the receive data buffer should be read out before receiving the
subsequent data is complete. If receiving the subsequent data is complete before the receive data buffer contents
are read out, the newly received data will overwrite the previous received data in the buffer.
In master mode, the SPBSY flag indicating the shift register status can be used in the same way while transfer-
ring data.
19-4
PCLK
SPICLKx
SDOx
Minimum 1/f
5.1 SDO
x and SPICLKx Change Timings when CPHA = 0
Seiko epson Corporation
Write
PCLK
S1C17624/604/622/602/621 TeChniCal Manual
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