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2
20 i
C MaSTeR (i2CM)
TXE setting
PCLK
T16 Ch.2 output
SCL0
SDA0
TXE
TBUSY
RTACK
RTDT[7:0]
Interrupt
RXE setting
PCLK
T16 Ch.2 output
SCL0
SDA0
RXE
RBUSY
RTACK
RTDT[7:0]
RBRDY/
Interrupt
PCLK
T16 Ch.2 output
SCL0
SDA0
STP
20.6
i2CM interrupts
The I2CM module includes a function for generating the following two different types of interrupts.
• Transmit buffer empty interrupt
• Receive buffer full interrupt
The I2CM module outputs one interrupt signal shared by the two above interrupt causes to the interrupt controller
(ITC).
20-6
Transmission start
A6/D7
D[7:0]
Figure 20.
5.7 Slave Address Transmission/Data Transmission
Receiving start
D7
Figure 20.
STP setting
Figure 20.
5.9 Stop Condition Generation
Seiko epson Corporation
Transmit data setting
A5/D6
D[7:0]
ACK transmitting
D6
D0
5.8 Data Receiving
Stop condition
S1C17624/604/622/602/621 TeChniCal Manual
Transmission end
ACK receiving
DIR/D0
ACK
Receiving end
ACK
I
2
C bus free
D[7:0]
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