Epson S1C17624 Technical Manual page 36

2 CPu
Classification
Logical operation and
and/c
and/nc
and
or
or/c
or/nc
or
xor
xor/c
xor/nc
xor
not
not/c
not/nc
not
Shift and swap sr
sa
sl
swap
Immediate extension ext
Conversion
cv.ab
cv.as
cv.al
cv.la
cv.ls
Branch
jpr
jpr.d
jpa
jpa.d
jrgt
jrgt.d
jrge
jrge.d
jrlt
jrlt.d
jrle
jrle.d
jrugt
jrugt.d
jruge
jruge.d
jrult
jrult.d
jrule
jrule.d
jreq
jreq.d
jrne
jrne.d
call
call.d
calla
calla.d
ret
ret.d
int
intl
reti
reti.d
brk
2-4
Mnemonic
%rd,%rs Logical AND between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
%rd,sign7 Logical AND of general-purpose register and immediate
%rd,%rs Logical OR between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
%rd,sign7 Logical OR of general-purpose register and immediate
%rd,%rs Exclusive OR between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
%rd,sign7 Exclusive OR of general-purpose register and immediate
%rd,%rs Logical inversion between general-purpose registers (1's complement)
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
%rd,sign7 Logical inversion of general-purpose register and immediate (1's complement)
%rd,%rs Logical shift to the right with the number of bits specified by the register
Logical shift to the right with the number of bits specified by immediate
%rd,imm7
%rd,%rs Arithmetic shift to the right with the number of bits specified by the register
%rd,imm7 Arithmetic shift to the right with the number of bits specified by immediate
%rd,%rs Logical shift to the left with the number of bits specified by the register
Logical shift to the left with the number of bits specified by immediate
%rd,imm7
%rd,%rs Bytewise swap on byte boundary in 16 bits
imm13 Extend operand in the following instruction
Converts signed 8-bit data into 24 bits
%rd,%rs
Converts signed 16-bit data into 24 bits
%rd,%rs
%rd,%rs Converts 32-bit data into 24 bits
%rd,%rs Converts 24-bit data into 32 bits
Converts 16-bit data into 32 bits
%rd,%rs
PC relative jump
sign10
%rb Delayed branching possible
Absolute jump
imm7
%rb Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign10 PC relative subroutine call
%rb Delayed call possible
imm7 Absolute subroutine call
%rb Delayed call possible
Return from subroutine
Delayed return possible
Software interrupt
imm5
imm5,imm3 Software interrupt with interrupt level setting
Return from interrupt handling
Delayed call possible
Debug interrupt
Seiko epson Corporation
Function
Branch condition: !Z & !(N ^ V)
Branch condition: !(N ^ V)
Branch condition: N ^ V
Branch condition: Z | N ^ V
Branch condition: !Z & !C
Branch condition: !C
Branch condition: C
Branch condition: Z | C
Branch condition: Z
Branch condition: !Z
S1C17624/604/622/602/621 TeChniCal Manual