Epson S1C17624 Technical Manual page 43

Flash Protect Bits (S1C17622)
address Bit
0x27ffc D15–4 reserved
(16 bits)
D3 Flash write-protect bit for 0x14000–0x17fff
D2 Flash write-protect bit for 0x10000–0x13fff
D1 Flash write-protect bit for 0xc000–0xffff
D0 Flash write-protect bit for 0x8000–0xbfff
address Bit
0x27ffe D15–4 reserved
(16 bits)
D3 Flash data-read-protect bit for 0x14000–0x17fff
D2 Flash data-read-protect bit for 0x10000–0x13fff
D1 Flash data-read-protect bit for 0xc000–0xffff
D0 reserved
Flash Protect Bits (S1C17602)
address Bit
0x17ffc D15–4 reserved
(16 bits)
D3 Flash write-protect bit for 0x14000–0x17fff
D2 Flash write-protect bit for 0x10000–0x13fff
D1 Flash write-protect bit for 0xc000–0xffff
D0 Flash write-protect bit for 0x8000–0xbfff
address Bit
0x17ffe D15–4 reserved
(16 bits)
D3 Flash data-read-protect bit for 0x14000–0x17fff
D2 Flash data-read-protect bit for 0x10000–0x13fff
D1 Flash data-read-protect bit for 0xc000–0xffff
D0 reserved
Flash Protect Bits (S1C17621)
address Bit
0x17ffc D15–2 reserved
(16 bits)
D1 Flash write-protect bit for 0xc000–0xffff
D0 Flash write-protect bit for 0x8000–0xbfff
address Bit
0x17ffe
D15–2 reserved
(16 bits)
D1 Flash data-read-protect bit for 0xc000–0xffff
D0 reserved
notes: • Be sure not to locate the area with data-read protection into the .data and .rodata sections.
• Be sure to set D0 of address 0x27ffe (S1C17624/604/622) or 0x17ffe (S1C17602/621) to 1. If
it is set to 0, the program cannot be booted.
3.2.4 access Control for the Flash Controller
The S1C17624/604/622/602/621 on-chip Flash memory is accessed via the exclusive Flash controller. A MISC reg-
ister is used to set the access condition for the Flash controller.
Setting number of read access cycles for the Flash controller
In order to read data from the Flash memory properly, set the appropriate number of read access cycles accord-
ing to the CCLK frequency using the FLCYC[2:0]/MISC_FL register.
FlaShC Control Register (MiSC_Fl)
Register name address Bit
FlaShC 0x5320 D15–10 –
Control Register
(16 bits) D9–8 –
(MiSC_Fl)
D7–3 –
D2–0 FlCYC[2:0] FLASHC read access cycle
S1C17624/604/622/602/621 TeChniCal Manual
Function
1 Writable
1 Writable
1 Writable
1 Writable
Function
1 Readable
1 Readable
1 Readable
Function
1 Writable
1 Writable
1 Writable
1 Writable
Function
1 Readable
1 Readable
1 Readable
Function
1 Writable
1 Writable
Function
1 Readable
name Function
reserved
reserved
reserved
Seiko epson Corporation
Setting init. R/W
– – –
0 Protected 1 R/W
0 Protected 1 R/W
0 Protected 1 R/W
0 Protected 1 R/W
Setting init. R/W
– – –
0 Protected 1 R/W
0 Protected 1 R/W
0 Protected 1 R/W
1 1 R/W Always set to 1.
Setting init. R/W
– – –
0 Protected 1 R/W
0 Protected 1 R/W
0 Protected 1 R/W
0 Protected 1 R/W
Setting init. R/W
– – –
0 Protected 1 R/W
0 Protected 1 R/W
0 Protected 1 R/W
1 1 R/W Always set to 1.
Setting init. R/W
– – –
0 Protected 1 R/W
0 Protected 1 R/W
Setting init. R/W
– – –
0 Protected 1 R/W
1 1 R/W Always set to 1.
Setting init. R/W
–
– 0x3
–
FLCYC[2:0] Read cycle 0x3 R/W
0x7–0x5 reserved
0x4 1 cycle
0x3 5 cycles
0x2 4 cycles
0x1 3 cycles
0x0 2 cycles
3 MeMORY MaP
Remarks
Remarks
Remarks
Remarks
Remarks
Remarks
Remarks
– – 0 when being read.
–
– – 0 when being read.
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