Epson S1C17624 Technical Manual page 44

3 MeMORY MaP
D[2:0] FlCYC[2:0]: FlaShC Read access Cycle Bits
Sets the number of read access cycles for the Flash controller.
Table 3.
FlCYC[2:0]
0x7–0x5
notes: • Be sure to avoid setting a number of read access cycles that exceeds the maximum allowable
CCLK frequency, as it may cause a malfunction.
• For maximum performance, set FLCYC[2:0] to 0x4.
3.3 internal RaM area
3.3.1 embedded RaM
The S1C17624/604 contains an 8K-byte RAM, the S1C17622/602 contains a 4K-byte RAM, and the S1C17621
contains a 2K-byte RAM.
RAM capacity
Address range
The RAM is accessed in one cycle for reading/writing and allows high-speed execution of the instruction codes
copied into it as well as storing variables and other data.
note: The 64-byte area at the end of the RAM (S1C17624/604: 0x1fc0–0x1fff, S1C17602: 0xfc0–0xfff)
is reserved for the on-chip debugger. When using the debug functions under application develop-
ment, do not access this area from the application program. This area can be used for applica-
tions of mass-produced devices that do not need debugging.
The S1C17624/604 enables the RAM size used to apply restrictions to 8KB, 4KB, or 2KB. The S1C17622 enables
the RAM size used to apply restrictions to 4KB or 2KB. For example, when using the S1C17624/604/622 to devel-
op an application for a built-in ROM model, you can set the RAM size to match that of the target model, preventing
creating programs that seek to access areas outside the RAM areas of the target product. The RAM size is selected
using IRAMSZ[2:0]/MISC_IRAMSZ register.
iRaM Size Select Register (MiSC_iRaMSZ)
Register name address Bit
iRaM Size 0x5326 D15–9 –
Select Register
(16 bits)
D8
(MiSC_iRaMSZ)
D7
D6–4 –
(S1C17624/604)
D3
D2–0 iRaMSZ[2:0] IRAM size select
3-6
2.4.1 Setting Read Access Cycles for the Flash Controller
number of read access cycles
0x4
0x3
0x2
0x1
0x0
Table 3. 3.1.1 Embedded RAM
S1C17624/604
8K bytes
0x0 to 0x1fff
name Function
reserved
DBaDR
Debug base address select
– reserved
reserved
–
reserved
Seiko epson Corporation
Reserved
1 cycle
5 cycles
4 cycles
3 cycles
2 cycles
S1C17622/602
4K bytes
0x0 to 0xfff
Setting
–
1 0x0 0 0xfffc00
–
–
–
IRAMSZ[2:0]
0x3
0x2
0x1
Other
S1C17624/604/622/602/621 TeChniCal Manual
CClK frequency
–
8.2 MHz max.
(Default: 0x3)
S1C17621
2K bytes
0x0 to 0x7ff
init. R/W Remarks
– – 0 when being read.
0 R/W
– – 0 when being read.
– – 0x1 when being read.
– – 0 when being read.
Size 0x1 R/W
2KB
4KB
8KB
reserved