Epson S1C17624 Technical Manual page 143

12 16-BiT PWM TiMeR (T16e)
notes: • The clock generator (CLG) must be configured to supply PCLK to the peripheral modules be-
fore running the timer.
• Make sure the counter is halted before setting the count clock.
T16e Ch.x interrupt Mask Register (T16e_iMSKx)
Register name address Bit
T16e Ch.x 0x530a D15–2 –
interrupt Mask
(16 bits)
Register D1
(T16e_iMSKx) D0
D[15:2] Reserved
D1 CBie: Compare B interrupt enable Bit
Enables or disables compare B match interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting CBIE to 1 enables compare B interrupt requests to the ITC. Setting it to 0 disables interrupts.
D0 Caie: Compare a interrupt enable Bit
Enables or disables compare A match interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting CAIE to 1 enables compare A interrupt requests to the ITC. Setting it to 0 disables interrupts.
T16e Ch.x interrupt Flag Register (T16e_iFlGx)
Register name address Bit
T16e Ch.x 0x530c D15–2 –
interrupt Flag (16 bits) D1
Register
D0
(T16e_iFlGx)
D[15:2] Reserved
D1 CBiF: Compare B interrupt Flag Bit
Indicates whether the cause of compare B interrupt has occurred or not.
1 (R): Cause of interrupt has occurred
0 (R): No cause of interrupt has occurred (default)
1 (W): Flag is reset
0 (W): Ignored
CBIF is a T16E interrupt flag that is set to 1 when the counter reaches the value set in the compare B
register. CBIF is reset by writing 1.
D0 CaiF: Compare a interrupt Flag Bit
Indicates whether the cause of compare A interrupt has occurred or not.
1 (R): Cause of interrupt has occurred
0 (R): No cause of interrupt has occurred (default)
1 (W): Flag is reset
0 (W): Ignored
CAIF is a T16E interrupt flag that is set to 1 when the counter reaches the value set in the compare A
register. CAIF is reset by writing 1.
12-10
name Function
reserved
CBie Compare B interrupt enable
Caie
Compare A interrupt enable
name Function
reserved
CBiF
Compare B interrupt flag
CaiF
Compare A interrupt flag
Seiko epson Corporation
Setting init. R/W
–
1 Enable 0 Disable
1 Enable 0 Disable
Setting init. R/W
–
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
– – 0 when being read.
0 R/W
0 R/W
Remarks
– – 0 when being read.
0 R/W Reset by writing 1.
0 R/W