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D1
MSSl: Master/Slave Mode Select Bit
Sets the SPI module to master or slave mode.
1 (R/W): Master mode
0 (R/W): Slave mode (default)
Setting MSSL to 1 selects master mode; setting it to 0 selects slave mode. Master mode performs data
transfer with the internal clock. In slave mode, data is transferred by inputting the clock from the master
device.
D0
SPen: SPi enable Bit
Enables or disables SPI module operation.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting SPEN to 1 starts the SPI module operation, enabling data transfer.
Setting SPEN to 0 stops the SPI module operation.
note: The SPEN bit should be set to 0 before setting the CPHA, CPOL, and MSSL bits.
S1C17624/604/622/602/621 TeChniCal Manual
Seiko epson Corporation
19 SPi
19-9
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