Epson S1C17624 Technical Manual page 72

D1 OSC1en: OSC1 enable Bit
Enables or disables OSC1 oscillator operations.
1 (R/W): Enabled (on)
0 (R/W): Disabled (off) (default)
When the system clock is switched to OSC1 immediately after the OSC1 oscillator circuit is turned on,
the OSC1 clock is supplied to the system after the OSC1 clock system supply wait time indicated below
(at a maximum) has elapsed.
OSC1 clock system supply wait time ≤ OSC1 oscillation start time (max.) + OSC1 oscilla-
tion
stabilization wait time (256 cycles)
note: The OSC1 oscillator cannot be stopped if the OSC1 clock is being used as the system clock.
D0 OSC3en: OSC3 enable Bit
Enables or disables OSC3 oscillator operations.
1 (R/W): Enabled (on)
0 (R/W): Disabled (off) (default)
note: The OSC3 oscillator cannot be stopped if the OSC3 clock is being used as the system clock.
noise Filter enable Register (OSC_nFen)
Register name address Bit
noise Filter 0x5062 D7–2 –
enable Register (8 bits)
D1
(OSC_nFen)
D0
D[7:2] Reserved
D1 RSTFe: Reset noise Filter enable Bit
Enables or disables the RESET input noise filter.
1 (R/W): Enabled (noise filtering) (default)
0 (R/W): Disabled (bypass)
This should normally be enabled.
D0 nMiFe: nMi noise Filter enable Bit
Enables or disables the NMI input noise filter.
1 (R/W): Enabled (noise filtering)
0 (R/W): Disabled (bypass) (default)
note: The S1C17624/604/622/602/621 has no external NMI input pin, but the watchdog timer NMI
request signal passes through the filter.
FOuT Control Register (OSC_FOuT)
Register name address Bit
FOuT Control 0x5064 D7–4 –
Register
(8 bits) D3–2 FOuThD
(OSC_FOuT)
D1
D0
D[7:4] Reserved
D[3:2] FOuThD[1:0]: FOuTh Clock Division Ratio Select Bits
Selects the HSCLK clock division ratio to set the FOUTH clock frequency.
S1C17624/604/622/602/621 TeChniCal Manual
name Function
reserved
RSTFe Reset noise filter enable
nMiFe
NMI noise filter enable
name Function
reserved
FOUTH clock division ratio select
[1:0]
FOuThe
FOUTH output enable
FOuT1e FOUT1 output enable
Seiko epson Corporation
7 ClOCK GeneRaTOR (ClG)
Setting init. R/W
–
1 Enable 0 Disable
1 Enable 0 Disable
Setting init. R/W
–
FOUTHD[1:0] Division ratio 0x0 R/W Source clock =
0x3 reserved
0x2 1/4
0x1 1/2
0x0 1/1
1 Enable 0 Disable
1 Enable 0 Disable
Remarks
– – 0 when being read.
1 R/W
0 R/W
Remarks
– – 0 when being read.
HSCLK
0 R/W
0 R/W
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