Epson S1C17624 Technical Manual page 46

3 MeMORY MaP
• 8-bit timers (T8F, 16-bit device)
• 16-bit timers (T16, 16-bit device)
• Interrupt controller (ITC, 16-bit device)
• SPI (SPI, 16-bit device)
• I C master (I2CM, 16-bit device)
2
• I 2 C slave (I2CS, 16-bit device)
3.5.2 internal Peripheral area 2 (0x5000–)
The internal peripheral area 2 beginning with address 0x5000 contains the I/O memory for the peripheral functions
listed below and this area can be accessed in one cycle.
• Clock timer (CT, 8-bit device)
• Stopwatch timer (SWT, 8-bit device)
• Watchdog timer (WDT, 8-bit device)
• Clock generator (CLG, 8-bit device)
• LCD driver (LCD, 8-bit device)
• 8-bit OSC1 timer (T8OSC1, 8-bit device)
• SVD circuit (SVD, 8-bit device)
• Power generator (VD1, 8-bit device)
• Real-time clock (RTC, 8-bit device) Available only in the S1C17624/604
• I/O port & port MUX (P, 8-bit device)
• 16-bit PWM timer (T16E, 16-bit device)
• MISC register (MISC, 16-bit device)
• IR remote controller (REMC, 16-bit device)
• A/D converter (ADC10, 16-bit device)
• R/F converter (RFC, 16-bit device)
• Display RAM (SEGRAM, 16-bit device)
• 16-bit PWM timers (T16A2, 16-bit device) Available only in the S1C17624/604
3.6 S1C17 Core i/O area
The 1K-byte area from address 0xfffc00 to address 0xffffff is the I/O area for the CPU core in which the I/O regis-
ters listed in the table below are located.
Peripheral address
S1C17 Core I/O 0xffff84
0xffff90
0xffffa0
0xffffb4
0xffffb8
0xffffbc
0xffffd0
See "Processor Information" in the "CPU" chapter for more information on IDIR. See the "On-chip Debugger
(DBG)" chapter for more information on other registers.
This area includes the S1C17 Core registers, in addition to those described above. For more information on these
registers, refer to the "S1C17 Core Manual."
3-8
Table 3. 6.1 I/O Map (S1C17 Core I/O Area)
Register name
IDIR Processor ID Register
DBRAM Debug RAM Base Register
DCR Debug Control Register
IBAR1 Instruction Break Address Register 1
IBAR2 Instruction Break Address Register 2
IBAR3 Instruction Break Address Register 3
IBAR4 Instruction Break Address Register 4
Seiko epson Corporation
Function
Indicates the processor ID.
Indicates the debug RAM base address.
Debug control
Instruction break address #1 setting
Instruction break address #2 setting
Instruction break address #3 setting
Instruction break address #4 setting
S1C17624/604/622/602/621 TeChniCal Manual