Epson S1C17624 Technical Manual page 183

17 Watchdog Timer (WDT)
17.1 WDT Module Overview
The S1C17624/604/622/602/621 includes a watchdog timer module (WDT) that uses the OSC1 oscillator as its
clock source. This timer is used to detect CPU runaway.
The features of WDT are listed below.
• 10-bit up counter
• Either reset or NMI can be generated if the counter overflows.
Figure 17.1.1 shows the WDT configuration.
CLG
OSC1
256 Hz
oscillator/divider
Reset
NMI
The WDT module generates an NMI or reset (selectable via software) to the CPU if not reset within 131,072/f
seconds (4 seconds when f
Reset WDT via software within this cycle to prevent NMI/resets, which in turn enables runaway detection for pro-
grams that do not pass through the handler routine.
17.2 Operation Clock
The WDT module uses the 256 Hz clock output by the CLG module as the operation clock. The CLG module
generates this operation clock by dividing the OSC1 clock into 1/128, resulting in a frequency of 256 Hz when
the OSC1 clock frequency is 32.768 kHz. The frequency described in this chapter will vary accordingly for other
OSC1 clock frequencies. The CLG module does not include a 256 Hz clock output control bit. The 256 Hz clock is
normally supplied to the WDT module when the OSC1 oscillation is on.
For detailed information on OSC1 oscillator control, see the "Clock Generator (CLG)" chapter.
17.3 WDT Control
17.3.1 nMi/Reset Mode Selection
WDTMD/WDT_ST register is used to select whether an NMI signal or a reset signal is output when WDT has not
been reset within the NMI/reset generation cycle.
To generate an NMI, set WDTMD to 0 (default). Set to 1 to generate a reset.
17.3.2 WDT Run/Stop Control
WDT starts counting when a value other than 0b1010 is written to WDTRUN[3:0]/WDT_CTL register and stops
when 0b1010 is written.
At initial reset, WDTRUN[3:0] is set to 0b1010 to stop WDT.
Since an NMI or reset may be generated immediately after running depending on the counter value, WDT should
also be reset concurrently (before running WDT), as explained in the following section.
S1C17624/604/622/602/621 TeChniCal Manual
WDTRUN[3:0]
Run/Stop control
Figure 17. 1.1 WDT Configuration
= 32.768 kHz).
OSC1
Seiko epson Corporation
WDTRST
Watchdog timer reset
10-bit counter
Interrupt
control circuit
17 WaTChDOG TiMeR (WDT)
Watchdog timer
NMI/reset
WDTMD
mode select
OSC1
17-1